Datasheet

DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 253 of 305
Register Name:
BSIM
Register Description:
BERT Status Interrupt Mask Register
Register Address:
110Fh + (10h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
BBED
—
—
BRA1
BRA0
BRLOS
BSYNC
Default
0
0
0
0
0
0
0
0
Bit 6: BERT Bit Error Detected Event (BBED)
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 3: BERT Receive All Ones Condition (BRA1)
0 = Interrupt masked.
1 = Interrupt enabled—interrupts on rising and falling edges.
Bit 2: BERT Receive All Zeros Condition (BRA0)
0 = Interrupt masked.
1 = Interrupt enabled—interrupts on rising and falling edges.
Bit 1: BERT Receive Loss Of Synchronization Condition (BRLOS)
0 = Interrupt masked.
1 = Interrupt enabled—interrupts on rising and falling edges.
Bit 0: BERT in Synchronization Condition (BSYNC)
0 = Interrupt masked.
1 = Interrupt enabled—interrupts on rising and falling edges.
10.7 Extended BERT Register Definitions
Table 10-29. Extended BERT Register Set
ADDR ABBR DESCRIPTION R/W
1400
BERT Control Register 3
R/W
1401
BERT Real-Time Status Register
R
1402
BERT Latched Status Register 1
R/W
1403
BERT Status Interrupt Mask 1
R/W
1404
BERT Latched Status Register 1
R/W
1405
BERT Status Interrupt Mask 2
R/W
Register Name:
BC3
Register Description:
BERT Control Register 3
Register Address:
1400h + (10h x (n-1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
- - - - - - 55OCT BALIGN
Default
0
0
0
0
0
0
0
0
Bit 1: 55 Octet Pattern (55OCT). This bit selects data pattern used by the transmit and receive circuits.
0 = 55 Octet Pattern disabled.
1 = 55 Octet pattern enabled, when Modified 55 Octet (Daly) Pattern is selected by
BC1.PSn register bits.
Bit 0: Byte Alignment to DS0 boundary(BALIGN).
A low-to-high transition causes the Transmit BERT pattern to be byte-aligned to the DS0 boundary. This
bit should be toggled from low to high when a pattern load is executed (
BC1.TC)