Datasheet

DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 234 of 305
Register Name:
TGCCS1, TGCCS2, TGCCS3, TGCCS4
Register Description:
Transmit Gapped Clock Channel Select Registers 1 to 4
Register Address:
1CCh, 1CDh, 1CEh, 1CFh + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TGCCS1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TGCCS2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TGCCS3
CH32 CH31 CH30 CH29 CH28 CH27 CH26
CH25
(F-bit)
TGCCS4 (E1
Mode Only)*
Bits 7 to 0: Transmit Channels 1 to 32 Gapped Clock Channel Select Bits (CH[1:32])
0 = no clock is present on TCHCLK during this channel time
1 = force a clock on TCHCLK during this channel time. The clock will be synchronous with TCLKn if the
elastic store is disabled, and synchronous with TSYSCLKn if the elastic store is enabled.
* Note that TGCCS4 has two functions:
When 2.048MHz backplane mode is selected, this register allows the user to enable the gapped clock on
TCHCLK for any of the 32 possible backplane channels.
When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not a clock is
generated on TCHCLK during the F-bit time:
TGCCS4.0 = 0, do not generate a clock during the F-bit.
TGCCS4.0 = 1, generate a clock during the F-bit.
In this mode TGCCS4.1 to TGCCS4.7 should be set to 0.
Register Name:
PCL1, PCL2, PCL3, PCL4
Register Description:
Per-Channel Loopback Enable Registers 1 to 4
Register Address:
1D0h, 1D1h, 1D2h, 1D3h + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
Bit #
7
6
5
4
3
2
1
0
Name
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
PCL1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
PCL2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
PCL3
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
PCL4 (E1
Mode Only)
Bits 7 to 0: Per-Channel Loopback Enable for Channels 1 to 32 (CH[1:32])
0 = Loopback disabled.
1 = Enable loopback. Source data from the corresponding receive channel.