Datasheet

DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 220 of 305
Register Name:
TCR4
Register Description:
Transmit Control Register 4
Register Address:
186h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
uALAW
BINV1
BINV0
TJBEN
TRAIM
TAISM
TC1
TC0
uALAW
BINV1
BINV0
TJBEN
—
—
—
—
Default
0
0
0
0
0
0
0
0
Bit 7: u-Law or A-Law Digital Milliwatt Code Select (uALAW)
0 = u-law code is inserted based on TDMWEx registers.
1 = A-law code is inserted based on TDMWEx registers.
Bits 6 and 5: Transmit Bit Inversion (BINV[1:0])
00 = No inversion.
01 = Invert framing.
10 = Invert signaling.
11 = Invert payload.
Bit 4: Transmit Jammed Bit 8 Suppression Enable (TJBEN)
0 = No stuffing enabled.
1 = Jammed Bit 8 Suppression enabled. This forces bit 8 to a one as determined by
TJBE1–4 registers
and bit 7 to a one in T1 signaling frames.
Bits 3: Transmit RAI Mode (TRAIM) (T1 Mode Only). Determines the pattern sent when TRAI (
TCR1.0) is
activated in ESF frame mode only.
0 = Transmit normal RAI when
TCR1.RAI = 1
1 = If T1 ESF mode, transmit RAI-CI (T1.403) when
TCR1.RAI = 1
Bits 2 : Transmit AIS Mode (TAISM) (T1 Mode Only). Determines the pattern sent when TAIS (
TCR1.1) is
activated.
0 = Transmit normal AIS (unframed all ones) upon activation with
TCR1.1.
1 = Transmit AIS-CI (T1.403) upon activation with
TCR1.1.
Bits 1 and 0 : Transmit Code Length Definition Bits (TC[1:0]) (T1 Mode Only)
TC1
TC0
Length Selected
0
0
5 bits
0
1
6 bits : 3 bits
1
0
7 bits
1
1
16 bits : 8 bits : 4 bits : 2 bits : 1 bit