Datasheet

DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 217 of 305
Register Name:
TCR3
Register Description:
Transmit Control Register 3
Register Address:
183h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
—
TCSS1
TCSS0
MFRS
TFM
IBPV
TLOOP
—
—
TCSS1
TCSS0
MFRS
—
IBPV
CRC4
Default
0
0
0
0
0
0
0
0
Bits 5 and 4 : Transmit Clock Source Select 1 and 0 (TCSS[1:0])
TCSS1
TCSS0
Transmit Clock Source
0
0
The TCLKn pin is always the source of transmit clock.
0 1
Switch to the clock present at RCLKn when the signal at the TCLKn pin fails to transition after
1 channel time.
1
0
Reserved.
1
1
Use the signal present at RCLKn as the transmit clock. The TCLKn pin is ignored (loop time).
Bit 3: Multiframe Reference Select (MFRS). This bit selects the source for the transmit formatter multiframe
boundary.
0 = Normal Operation. Transmit multiframe boundary is determined by 'line-side' counters referenced to
TSYNCn when TSYNCn is an input. Free-running when TSYNCn is an output.
1 = Pass-Forward Operation. Tx multiframe boundary determined by 'system-side' counters referenced to
TSSYNCIOn (input mode3), which is then passed forward to the line side clock domain. This mode can
only be used when the transmit elastic store is enabled with a synchronous backplane (i.e., no frame slips
allowed). This mode must be used to allow Tx hardware signaling insertion while the Tx elastic store is
enabled.
Bit 2: Transmit Frame Mode Select (TFM) (T1 Mode Only)
0 = ESF framing mode.
1 = D4 framing mode.
Bit 1: Insert BPV (IBPV). A 0-to-1 transition on this bit will cause a single Bipolar Violation (BPV) to be inserted
into the transmit data stream. Once this bit has been toggled from a 0 to a 1, the device waits for the next
occurrence of three consecutive ones to insert the BPV. This bit must be cleared and set again for a subsequent
error to be inserted.
Bit 0 (T1 Mode): Transmit Loop Code Enable (TLOOP). See Section
9.9.15 for details.
0 = Transmit data normally.
1 = Replace normal transmitted data with repeating code as defined in registers
T1TCD1 and T1TCD2.
Bit 0 (E1 Mode): CRC-4 Recalculate (CRC4R)
0 = Transmit CRC-4 generation and insertion operates in normal mode.
1 = Transmit CRC-4 generation operates according to G.706 Intermediate Path Recalculation method.