Datasheet

DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 205 of 305
Register Name:
TDDS1, TDDS2, TDDS3
Register Description:
Transmit DDS Zero Code Registers 1 to 3
Register Address:
108h, 109h, 10Ah + (200h x (n - 1)) : where n = 1 to 4
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TDDS1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TDDS2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TDDS3
The Transmit DDS Zero Code Registers (TDDS1–3) select which of the 24 T1 channels to insert DDS zero code
stuffing. These registers are enabled by
T1.TCR2.TDDSEN.
Bits 7 to 0: Transmit Channels 1 to 24 DDS Zero Code Control Bits (CH[1:32])
0 = Do not affect data in this channel.
1 = Replace the channel with DDS Zero Code stuffing if the channel is all zeros.
Register Name:
T1TFDL
Register Description:
Transmit FDL Register
Register Address:
162h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
TFDL7
TFDL6
TFDL5
TFDL4
TFDL3
TFDL2
TFDL1
TFDL0
Default
0
0
0
0
0
0
0
0
Note: Also used to insert Fs framing pattern in D4 framing mode.
The Transmit FDL Register (T1TFDL) contains the Facility Data Link (FDL) information that is to be inserted on a
byte basis into the outgoing T1 data stream. The LSB is transmitted first. In D4 mode, only the lower six bits are
used.
Bit 7: Transmit FDL Bit 7 (TFDL7). MSB of the Transmit FDL Code.
Bit 6: Transmit FDL Bit 6 (TFDL6)
Bit 5: Transmit FDL Bit 5 (TFDL5)
Bit 4: Transmit FDL Bit 4 (TFDL4)
Bit 3: Transmit FDL Bit 3 (TFDL3)
Bit 2: Transmit FDL Bit 2 (TFDL2)
Bit 1: Transmit FDL Bit 1 (TFDL1)
Bit 0: Transmit FDL Bit 0 (TFDL0). LSB of the Transmit FDL Code.