Datasheet

DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 194 of 305
Register Name:
RRTS5
Register Description:
Receive Real-Time Status Register 5 (HDLC-64)
Register Address:
0B4h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
—
PS2
PS1
PS0
—
—
RHWM
RNE
Default
0
0
0
0
0
0
0
0
Note: All bits in this register are real time.
Bits 6 to 4: Receive Packet Status (PS[2:0]). These are real-time bits indicating the status as of the last read of
the receive FIFO.
PS2
PS1
PS0
PACKET STATUS
0 0 0
In Progress: End of message has not yet been reached.
0 0 1
Packet OK: Packet ended with correct CRC codeword.
0 1 0
CRC Error: A closing flag was detected, preceded by a corrupt CRC codeword.
0 1 1
Abort: Packet ended because an abort signal was detected (7 or more ones in a row).
1 0 0
Overrun: HDLC controller terminated reception of packet because receive FIFO is full.
Bit 1: Receive FIFO Above High Watermark Condition (RHWM). Set when the receive 64-byte FIFO fills beyond
the high watermark as defined by the Receive HDLC FIFO Control Register (RHFC). This is a real-time bit.
Bit 0: Receive FIFO Not Empty Condition (RNE). Set when the receive 64-byte FIFO has at least one byte
available for a read. This is a real-time bit.
Register Name:
RHPBA
Register Description:
Receive HDLC-64 Packet Bytes Available Register
Register Address:
0B5h + (200h x (n - 1)) : where n = 1 to 4
Bit #
7
6
5
4
3
2
1
0
Name
MS
RPBA6
RPBA5
RPBA4
RPBA3
RPBA2
RPBA1
RPBA0
Default
0
0
0
0
0
0
0
0
Bit 7: Message Status (MS)
0 = Bytes indicated by RPBA0 through RPBA6 are the end of a message. Host must check the HDLC
Status register for details.
1 = Bytes indicated by RPBA0 through RPBA6 are the beginning or continuation of a message. The host
does not need to check the HDLC Status. The MS bit will return to a value of ‘1’ when the Rx HDLC FIFO
is empty.
Bits 6 to 0: Receive FIFO Packet Bytes Available Count (RPBA[6:0]). RPBA0 is the LSB.