Datasheet

DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 112 of 305
10.1.4 BERT Register List
Table 10-5. BERT Register List
Note that only the BERT 1 address is presented here. The same set of registers definitions applies for BERTs 2 to 4 in accordance with the
DS26514 map offsets. BERT offset is [1100+ (n - 1) x 10 hex], where n designates the BERT channel in question.
BERT REGISTER LIST
ADDRESS NAME DESCRIPTION
R/W
1100h BAWC BERT Alternating Word Count Rate Register R
1101h BRP1 BERT Repetitive Pattern Set Register 1 R/W
1102h BRP2 BERT Repetitive Pattern Set Register 2 R/W
1103h BRP3 BERT Repetitive Pattern Set Register 3 R/W
1104h BRP4 BERT Repetitive Pattern Set Register 4 R/W
1105h BC1 BERT Control Register 1 R/W
1106h BC2 BERT Control Register 2 R/W
1107h BBC1 BERT Bit Count Register 1 R
1108h BBC2 BERT Bit Count Register 2 R
1109h BBC3 BERT Bit Count Register 3 R
110Ah BBC4 BERT Bit Count Register 4 R
110Bh BEC1 BERT Error Count Register 1 R
110Ch BEC2 BERT Error Count Register 2 R
110Dh BEC3 BERT Error Count Register 3 R
110Eh BSR BERT Latched Status Register R
110Fh BSIM BERT Status Interrupt Mask Register R/W
1400h
BC3
BERT Control Register 3
R/W
1401h
BRSR
BERT Real-Time Status Register
R
1402h
BLSR1
BERT Latched Status Register 1
R/W
1403h
BSIM1
BERT Status Interrupt Mask Register 1
R/W
1404h
BLSR2
BERT Latched Status Register 2
R/W
1405h
BSIM2
BERT Status Interrupt Mask Register 2
R/W