Datasheet

DS26504 T1/E1/J1/64KCC BITS Element
85 of 129
13.7 LIU Control Registers
Register Name:
LIC1
Register Description:
Line Interface Control 1
Register Address:
30h
Bit # 7 6 5 4 3 2 1 0
Name L2 L1 L0 EGL JAS JABDS DJA TPD
Default 0 0 0 0 0 0 0 0
HW
Mode
L2
PIN 13
L1
PIN 12
L0
PIN 11
0 0 0 0 1
Bit 0: Transmit Power-Down (TPD)
0 = powers down the transmitter and three-states the TTIP and TRING pins
1 = normal transmitter operation
Bit 1: Disable Jitter Attenuator (DJA)
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Bit 2/Jitter Attenuator Buffer Depth Select (JABDS)
0 = 128 bits
1 = 32 bits (use for delay-sensitive applications)
Bit 3: Jitter Attenuator Select (JAS)
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Bit 4: Receive Equalizer Gain Limit (EGL). This bit controls the sensitivity of the receive equalizer.
T1 Mode: 0 = -36dB (long haul)
1 = -15dB (limited long haul)
E1 Mode: 0 = -43dB (long haul)
1 = -12dB (short haul)
Bits 5, 6, 7: Line Build-Out Select (L0 to L2). When using the internal termination, the user needs only to select 000 for 75Ω
operation or 001 for 120Ω operation. This selects the proper voltage levels for 75Ω or 120Ω operation. Using TT0, TT1, and
TT2 of the LICR4 register, users can then select the proper internal source termination. Line build-outs 100 and 101 are for
backwards compatibility with older products only.
E1 Mode
L2 L1 L0 APPLICATION N (Note 1) RETURN LOSS Rt (Note 1)
0 0 0 75Ω normal 1:2 N.M. 0
0 0 1 120Ω normal 1:2 N.M. 0
1 0 0 75Ω with high return loss (Note 2) 1:2 21dB 6.2Ω
1 0 1 120Ω with high return loss (Note 2) 1:2 21dB 11.6Ω
N.M. = Not meaningful
Note 1: Transformer turns ratio.
Note 2: TT0, TT1, and TT2 of the LIC4 register must be set to zero in this configuration.