Datasheet

DS26504 T1/E1/J1/64KCC BITS Element
36 of 129
Register Name:
TPCR1
Register Description:
Transmit PLL Control Register 1
Register Address:
09h
Bit # 7 6 5 4 3 2 1 0
Name TPLLOFS1 TPLLOFS0 PLLOS TPLLIFS1 TPLLIFS0 TPLLSS TCSS1 TCSS0
Default 0 0 0 0 0 0 0 0
HW
Mode
0 0 0 0 0 0
TCSS1
PIN 31
TCSS0
PIN 63
For more information on all the bits in the Transmit PLL control register, refer to Figure 3-3.
Bits 0 and 1: Transmit Clock (TX CLOCK) Source Select (TCSS[0:1]). These bits control the output of the TX PLL
Clock Mux function. See
Figure 3-3.
TCSS1 TCSS0
TRANSMIT CLOCK (TX CLOCK) SOURCE
(See
Figure 3-3)
0 0 The TCLK pin is the source of transmit clock.
0 1 The PLL_CLK is the source of transmit clock.
1 0 The scaled signal present at MCLK as the transmit clock.
1 1 The signal present at RCLK is the transmit clock.
Bit 2: Transmit PLL_CLK Source Select (TPLLSS). Selects the reference signal for the TX PLL.
0 = Use the recovered network clock. This is the same clock available at the RCLK pin (output).
1 = Use the externally provided clock present at the TCLK pin.
Bit 3 and 4: Transmit PLL Input Frequency Select (TPLLIFS[0:1]). These bits, along with TPLLIFS2 (TPCR2.0), are
used to indicate the reference frequency being input to the TX PLL.
TPLLIFS2
(TPCR2.0)
TPLLIFS1 TPLLIFS0
TX PLL INPUT
FREQUENCY
0 0 0 1.544MHz
0 0 1 2.048MHz
0 1 0 64kHz
0 1 1 6312kHz
1 0 0 8kHz
1 0 1 19.44MHz
Bit 5: PLL_OUT Select (PLLOS). This bit selects the source for the PLL_OUT pin. See Figure 3-3.
0 = PLL_OUT is sourced directly from the TX PLL.
1 = PLL_OUT is the output of the TX PLL mux.
Bits 6 and 7: Transmit PLL Output Frequency Select (TPLLOFS[0:1]). These bits, along with TPLLOFS1 (TPCR2.1),
are used to select the TX PLL output frequency.
TPLLOFS2
(TPCR2.1)
TPLLOFS1 TPLLOFS0
TX PLL OUTPUT
FREQUENCY
0 0 0 1.544MHz
0 0 1 2.048MHz
0 1 0 64kHz
0 1 1 6312kHz
1 0 0 8kHz
1 0 1 19.44MHz