Datasheet

DS26504 T1/E1/J1/64KCC BITS Element
28 of 129
6.6 MCLK Pre-Scaler
Table 6-7. MCLK Pre-Scaler for T1 Mode
MPS1
PIN 16
MPS0
PIN 15
JACKS0
PIN 46
MCLK
(MHz)
0 0 0 1.544
0 1 0 3.088
1 0 0 6.176
1 1 0 12.352
0 0 1 2.048
0 1 1 4.096
1 0 1 8.192
1 1 1 16.384
Table 6-8. MCLK Pre-Scaler for E1 Mode
MPS1
PIN 16
MPS0
PIN 15
JACKS0
PIN 46
MCLK
(MHz)
0 0 0 2.048
0 1 0 4.096
1 0 0 8.192
1 1 0 16.384
6.7 Payload Clock Output
The TCLKO and RCLK pins can output a clock with the F-Bit (T1) or the TS0 and TS16 (E1) bit
position gapped out. This function is only available in T1 or E1 mode. This is useful in basic transceiver
applications where a payload or “demand” clock is needed. In Hardware Mode, the payload clock output
is selected by the L0, L1, and L2 line build-out pins. In Hardware Mode, this function is only available in
certain build-out modes. See the line build-out tables in Section 6.3 for selecting the payload clock mode.