Datasheet

DS26504 T1/E1/J1/64KCC BITS Element
128 of 129
21. REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
070105 New product release. —
081105 Corrected the polarity of the TAIS pin when operating in Hardware mode. 19, 29
101805
Changed Section 13.4 to read “2.048 x 2
N
(where N = 1 to 3)” instead of
“2.048 x N (where N = 1 to 4).”
020906
Section 13.3.1, Section 13.3.2, SR1 Bits 1 and 2: Clarified the open circuit and
short circuit wording.
Figure 13-1: Corrected the capacitor value from 1μF to 10μF.
Replaced Figure 13-4 and 13-5 (added Table 13-1 and Table 13-2) to show
two different types of recommended protection circuit interfaces.
Added package drawing link to Package Information section, along with
updated package drawing.
Removed reference to E1RCR and E1TCR bit 3 (this bit functionality has been
moved to the MCREG).
48
053107
Replaced Figure 13-4 and Figure 13-5 to show 10μF cap on TTIP.
92, 93
100507
In the Absolute Maximum Ratings (Section 19), added Note 1: Specifications
at -40
° C are guaranteed by design GBD and not production tested. to
Operating Temp Range for DS26504LN. Renumbered notes for Table 19-1 to
Table 19-5.
113, 114
Clarified RITD and TITD descriptions.
16, 17
For E1TS description, changed 0 = 120Ω and 1 = 75Ω to 0 = 75Ω and 1 =
120Ω.
19
121707
Corrected Note 2 in the LIC1[7:5] register description to include TT2 along
with TT0 and TT1.
84
042208
In Section 13, corrected the wording to clearly indicate that different
transformers are required for T1, J1, E1, and 6312kHz modes and for 64KCC
mode.
79
072308
In Table 7-2, changed address 21 and 22 from “—” to “SR5” and “IMR5”;
added bit 4 (SR5) to IIR.
32, 39