Datasheet

DS26503 T1/E1/J1 BITS Element
Figure 19-11. Transmit Timing, T1/E1
TSER
TS_8K_4
1
t
D2
t
HD
t
SU
TS_8K_4
2
t
SU
t
F
t
R
TCLK
t
t
CL
t
CH
CP
TX CLOCK
3
PLL_OUT
t
D3
RCLK, JA CLOCK
4
(REFER TO THE TRANSMIT PLL BLOCK DIAGRAM, Figure 3-3.)
NOTE 1: TS IN OUTPUT MODE.
NOTE 2: TS IN INPUT MODE.
NOTE 3: TX CLOCK IS THE INTERNAL CLOCK THAT DRIVES THE TRANSMIT SECTION. THE
SOURCE OF THIS SIGNAL DEPENDS ON THE CONFIGURATION OF THE TRANSMIT PLL. IF TX
CLOCK IS GENERATED BY THE TRANSMIT PLL (CONVERSION FROM ANOTHER CLOCK RATE)
THEN THE USER SHOULD OUTPUT THAT SIGNAL ON THE PLL_OUT PIN AND USE THAT SIGNAL
TO REFERENCE TSER AND TS IF TS IS IN THE INPUT MODE.
NOTE 4: RCLK (THE RECOVERED LINE CLOCK) AND JA CLOCK (AN INTERNAL CLOCK DERIVED
FROM MCLK) MAY BE SELECTED AS THE SOURCE FOR THE TRANSMIT PLL OR USED
UNCONVERTED FOR TX CLOCK.
TS
1
TS
2
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