Datasheet

DS26503 T1/E1/J1 BITS Element
Bit #
Register Name:
LIC4
Register Description:
Line Interface Control 4
Register Address:
33h
7 6 5 4 3 2 1 0
Name MPS1 MPS0 TT2 TT1 TT0 RT2 RT1 RT0
Default 0 0 0 0 0 0 0 0
HW
Mode
MPS1
PIN 16
MPS0
PIN 15
— — — — — —
Bits 0 to 2: Receive Termination Select (RT0 to RT2)
RT2 RT1 RT0
INTERNAL RECEIVE
TERMINATION CONFIGURATION
0 0 0 Internal Receive-Side Termination Disabled
0 0 1 Internal Receive-Side 75Ω Enabled
0 1 0 Internal Receive-Side 100Ω Enabled
0 1 1 Internal Receive-Side 120Ω Enabled
1 0 0 Internal Receive-Side 110Ω Enabled
1 0 1
Internal Receive-Side Termination Disabled
1 1 0 Internal Receive-Side Termination Disabled
1 1 1 Internal Receive-Side Termination Disabled
Bits 3 to 5: Transmit Termination Select (TT0 to TT2)
TT2 TT1 TT0
INTERNAL TRANSMIT
TERMINATION CONFIGURATION
0 0 0 Internal Transmit-Side Termination Disabled
0 0 1 Internal Transmit-Side 75Ω Enabled
0 1 0 Internal Transmit-Side 100Ω Enabled
0 1 1 Internal Transmit-Side 120Ω Enabled
1 0 0 Internal Transmit-Side 110Ω Enabled
1 0 1 Internal Transmit-Side Termination Disabled
1 1 0 Internal Transmit-Side Termination Disabled
1 1 1 Internal Transmit-Side Termination Disabled
Bits 6 and 7: MCLK Pre-Scaler (MPS0 to MPS1) (T1 Mode)
MCLK (MHz) MPS1 MPS0 JACKS1 (LIC2.3) JACKS0 (LIC2.7)
1.544 0 0 0 0
3.088 0 1 0 0
6.176 1 0 0 0
12.352 1 1 0 0
0 1 1
2.048 0 0 1 0
4.096 0 1 1 0
8.192 1 0 1 0
16.384 1 1 1 0
12.80 0
Bits 6 and 7: MCLK Pre-Scaler (MPS0 to MPS1) (E1 Mode)
MCLK (MHz) MPS1 MPS0 JACKS (LIC2.3) JACKS0 (LIC2.7)
2.048 0 0 0 0
4.096 0 1 0 0
8.192 1 0 0 0
12.80 0 0 0 1
16.384 1 1 0 0
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