Datasheet

DS26503 T1/E1/J1 BITS Element
TABLE OF CONTENTS
1. FEATURES ....................................................................................................................................7
1.1 G
ENERAL .....................................................................................................................................7
1.2 L
INE INTERFACE ...........................................................................................................................7
1.3 J
ITTER ATTENUATOR (T1/E1 MODES ONLY) ..................................................................................7
1.4 F
RAMER/FORMATTER ...................................................................................................................8
1.5 T
EST AND DIAGNOSTICS ...............................................................................................................8
1.6 C
ONTROL PORT............................................................................................................................8
2. SPECIFICATIONS COMPLIANCE.................................................................................................9
3. BLOCK DIAGRAMS.....................................................................................................................11
4. PIN FUNCTION DESCRIPTION...................................................................................................14
4.1 T
RANSMIT PLL ...........................................................................................................................14
4.2 T
RANSMIT SIDE ..........................................................................................................................14
4.3 R
ECEIVE SIDE ............................................................................................................................15
4.4 C
ONTROLLER INTERFACE............................................................................................................16
4.5 JTAG.........................................................................................................................................21
4.6 L
INE INTERFACE .........................................................................................................................21
4.7 P
OWER ......................................................................................................................................22
5. PINOUT ........................................................................................................................................23
6. HARDWARE CONTROLLER INTERFACE .................................................................................26
6.1 T
RANSMIT CLOCK SOURCE .........................................................................................................26
6.2 I
NTERNAL TERMINATION..............................................................................................................26
6.3 L
INE BUILD-OUT .........................................................................................................................27
6.4 R
ECEIVER OPERATING MODES....................................................................................................27
6.5 T
RANSMITTER OPERATING MODES ..............................................................................................28
6.6 MCLK P
RE-SCALER ...................................................................................................................28
6.7 O
THER HARDWARE CONTROLLER MODE FEATURES ....................................................................29
7. PROCESSOR INTERFACE .........................................................................................................30
7.1 PARALLEL PORT FUNCTIONAL DESCRIPTION................................................................................30
7.2 SPI S
ERIAL PORT INTERFACE FUNCTIONAL DESCRIPTION............................................................30
7.2.1 Clock Phase and Polarity......................................................................................................30
7.2.2 Bit Order................................................................................................................................30
7.2.3 Control Byte ..........................................................................................................................30
7.2.4 Burst Mode............................................................................................................................30
7.2.5 Register Writes .....................................................................................................................31
7.2.6 Register Reads .....................................................................................................................31
7.3 R
EGISTER MAP...........................................................................................................................32
7.3.1 Power-Up Sequence.............................................................................................................34
7.3.2 Test Reset Register ..............................................................................................................34
7.3.3 Mode Configuration Register ................................................................................................35
7.4 I
NTERRUPT HANDLING ................................................................................................................38
7.5 S
TATUS REGISTERS....................................................................................................................38
7.6 I
NFORMATION REGISTERS ...........................................................................................................39
7.7 I
NTERRUPT INFORMATION REGISTERS .........................................................................................39
8. T1 FRAMER/FORMATTER CONTROL REGISTERS .................................................................40
8.1 T1 C
ONTROL REGISTERS............................................................................................................40
2 of 122