Datasheet

DS26503 T1/E1/J1 BITS Element
14 of 122
4. PIN FUNCTION DESCRIPTION
4.1 Transmit PLL
NAME TYPE FUNCTION
PLL_OUT O
Transmit PLL Output. This pin can be selected to output the 1544kHz,
2048kHz, 64kHz, or 6312kHz output from the internal TX PLL or the internal
signal, TX CLOCK. See Figure 3-3 and Figure 3-4.
TCLK I
Transmit Clock Input. A 64kHz, 1.544MHz, 2.048MHz, or 6312kHz primary
clock. May be selected by the TX PLL mux to either directly drive the transmit
section or be converted to one of the other rates prior to driving the transmit
section. See Figure 3-3
and Figure 3-4.
4.2 Transmit Side
NAME TYPE FUNCTION
TSER I
Transmit Serial Data. Source of transmit data sampled on the falling edge of
TX CLOCK (an internal signal). See Figure 3-3
, Figure 3-4, and Figure 19-11
(transmit timing diagram).
TS I/O
TSYNC. When in input mode, this pin is sampled on the falling edge of TX
CLOCK (an internal signal) and a pulse at this pin will establish either frame or
multiframe boundaries for the transmit side. See Figure 3-1
and Figure 19-11.
In output mode, the pin is updated on the rising edge of TX CLOCK (an
internal signal) and can be programmed to output a frame or multiframe sync
pulse useful for aligning data. See Figure 3-1
and Figure 19-11.
TCLKO O
Transmit Clock Output. Buffered clock that is used to clock data through the
transmit-side formatter (i.e., either TCLK or RCLK).
TPOSO O
Transmit Positive-Data Output. In T1 or E1 mode, updated on the rising edge
of TCLKO with the bipolar data out of the transmit-side formatter. Can be
programmed to source NRZ data via the output-data format (IOCR1.0) control
bit. In 6312kHz mode, this pin is low.
TNEGO O
Transmit Negative-Data Output. In T1 or E1 mode, updated on the rising
edge of TCLKO with the bipolar data out of the transmit-side formatter. In
6312kHz mode, this pin is low.