Datasheet

DS26502
124 of 125
21. REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
070904 New product release. —
032405
Updated Table 2-1 and Table 2-2.
Updated Figure 3-1.
Replaced the older recommended LIU circuits in Section 13.8 with newer
versions (Figure 13-4 and Figure 13-5, Table 13-1 and Table 13-2)
Added timing information to Table 20-4 and updated Figure 20-11.
081105
Corrected the bit order of the TPCR register (bits 3 and 4 were reversed).
Corrected the polarity for the TAIS pin description in hardware operation
mode.
Added values to Table 19-2.
101805
Changed Section 13.4 to read “2.048 x 2
N
(where N = 1 to 3)” instead of
“2.048 x N (where N = 1 to 4)”
Edited Figure 3-4 to show 12.8MHz clock option and added references
throughout relevant sections of the document.
Added JACKS1 bit to LIC2.7—This feature is available in Rev B1 and later.
020906
Section 13.3.1, Section 13.3.2, SR1 Bits 1 and 2: Clarified the open circuit and
short circuit wording.
Added package drawing link to Package Information section, along with
updated package drawing.
Removed reference to E1RCR and E1TCR bit 3 (this bit functionality
has been moved to the MCREG).
48
053107
Replaced Figure 13-4 and Figure 13-5 to show 10μF cap on TTIP.
90, 91
100507
In the Absolute Maximum Ratings (Section 19), added Note 1:
Specifications at -40
° C are guaranteed by design GBD and not
production tested. to Operating Temp Range for DS26502LN.
Renumbered notes for Table 19-1 to Table 19-5.
111, 112
Clarified RITD and TITD descriptions.
16
For E1TS description, changed 0 = 120Ω and 1 = 75Ω to 0 = 75Ω and
1 = 120Ω.
19
121707
Corrected Note 2 in the LIC1[7:5] register description to include TT2
along with TT0 and TT1.
82
042208
In Section 13, corrected the wording to clearly indicate that different
transformers are required for T1, J1, E1, and 6312kHz modes and for
64KCC mode.
77