Datasheet

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
9 of 101
3 BLOCK DIAGRAMS
Figure 3-1. Block Diagram
Line Drivers
Optional
Termination
Filter
Peak Detector
Clock/Data
Recovery
Analog Loopback
Wave Shaping
Remote Loopback (Dual Mode)
Local Loopback
Jitter Attenuator
Remote Loopback
Receive Logic
Transmit Logic
VCO/PLL
Jitter Attenuator
MUX
2.048MHz to
1.544MHz PLL
MUX
Unframed All
Ones Insertion
RRING
RTIP
TRING
TTIP
T1CLK E1CLK
RPOS/RDAT
RNEG/CV
RCLK
TPOS/TDAT
TNEG
TCLK
Master Clock
Adapter
JTAG PORT
Control
and
Interrupt
Port Interface
CLKE
RDB/RWB
RDY/ACKB/SDO
MOTEL
ASB/ALE/SCLK
D7/AD7/
BSWB
A0 to A4
D0 to D6/
AD0 to AD6
CSB
INTB
JTRSTB
JTMS
JTCLK
JTDI
JTDO
MCLK
T1CLK E1CLK
88
TYPICAL OF ALL 8 CHANNELS
OE
MODESEL
WRB/DSB/SDI
85
Reset
RLOS
Reset
MUX
DS26303