Datasheet

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
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Table 7-2. ID Code Structure
MSB LSB
Version
Contact Factory
Device ID JEDEC 1
4 bits 16 bits 00010100001 1
Table 7-3 Device ID Codes
PART DIE REV JTAG REV JTAG ID
DS26303-075 A1 0h 0080h
DS26303-125 A1 0h 0081h
7.3 Test Registers
IEEE 1149.1 requires a minimum of two test registers: the Bypass Register and the Boundary Scan Register. An
optional test register has been included with the DS26303 design. This test register is the Identification Register
and is used with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
7.3.1 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells
and is n bits in length.
7.3.2 Bypass Register
This is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions that provide a short
path between JTDI and JTDO.
7.3.3 Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. See
Table
7-2
and Table 7-3 for more information about bit usage.