Datasheet

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

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7 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT

The DS26303 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and

EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26303 contains the

following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture:

• Test Access Port (TAP)

• TAP Controller

• Instruction Register

• Bypass Register

• Boundary Scan Register

• Device Identification Register

Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE

1149.1a-1993, and IEEE 1149.1b-1994. The Test Access Port has the necessary interface pins: JTRSTB, TCLK,

JTMS, JTDI, and JTDO. See the pin descriptions for details. For the latest BSDL file go to

www.maxim-ic.com/tools/bsdl/ and search for DS26303.

Figure 7-1. JTAG Functional Block Diagram

INSTRUCTION

JTD1

JTMS

TCLK

JTRSTB

JTDO

TEST ACCESS PORT

CONTROLLER

MUX

10kΩ

SELECT

OUTPUT ENABLE

10k

BYPASS REGISTER

IDENTIFICATION

BOUNDARY SCAN