Datasheet

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
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6 FUNCTIONAL DESCRIPTION
6.1 Power-Up and Reset
Internal power-on-reset circuitry generates a reset during power-up. All registers are reset to the default values.
Writing to the software-reset register generates at least a 1μs reset cycle, which has the same effect as the power-
up reset.
6.2 Master Clock
The receiver uses the MCLK as a reference for clock recovery, jitter attenuation, and generating RCLKn during
LOS. The DS26303 requires 2.048MHz ±50ppm or 1.544MHz ±50ppm or a multiple thereof. The AIS transmission
uses MCLK for transmit all-ones condition. See register
MC to set desired incoming frequency. If the PLLE bit is
not set, MCLK is whatever the incoming frequency is.
MCLK or RCLK can be used to output CLKA. Register
CCR is used to select the clock generated for CLKA and the
TECLK. Any RCLKn can be selected as an input to the clock generator using this same register. For a detailed
description of selections available, see
Figure 6-1.
Figure 6-1. Prescaler PLL and Clock Generator
Pre
Scaler
PLL
CLK
GEN
E1CLK
T1CLK
FREQSMPS1..0
PLLE
PCLKS2..0
PCLKI1..0
RLCK1..8
PLLE
CLKA3..0
CLKAI
CLKA
RLOS16
CLKAE
TECLK
RLOS1
TECLKE
TECLKI
TECLKS
MCLK