Datasheet

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
48 of 101
Register Name:
BPCR1
Register Description:
BERT Pattern Configuration Register 1
Register Address:
02h
Bit # 7 6 5 4 3 2 1 0
Name — QRSS PTS PLF4 PLF3 PLF2 PLF1 PLF0
Default 0 0 0 0 0 0 0 0
Bit 6: QRSS Enable (QRSS). When 0, the pattern generator configuration is controlled by PTS, PLF[4:0], and
PTF[4:0], and BSP[31:0]. When 1, the pattern generator configuration is forced to a PRBS pattern with a
generating polynomial of x
20
+ x
17
+ 1. The output of the pattern generator is forced to one if the next 14 output bits
are all 0.
Bit 5: Pattern Type Select (PTS). When 0, the pattern is a PRBS pattern. When 1, the pattern is a repetitive
pattern.
Bits 4 to 0: Pattern Length Feedback (PLF[4:0]). These bits control the “length” feedback of the pattern
generator. The length feedback is from bit n of the pattern generator (n = PLF[4:0] +1). For a PRBS signal, the
feedback is an XOR of bit n and bit y. For a repetitive pattern the feedback is bit n.
Register Name:
BPCR2
Register Description:
BERT Pattern Configuration Register 2
Register Address:
03h
Bit # 7 6 5 4 3 2 1 0
Name — — — PTF4 PTF3 PTF2 PTF1 PTF0
Default 0 0 0 0 0 0 0 0
Bits 4 to 0: Pattern Tap Feedback (PTF[4:0]). These bits control the PRBS “tap” feedback of the pattern
generator. The tap feedback is from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored when
programmed for a repetitive pattern. For a PRBS signal, the feedback is an XOR of bit n and bit y.