Datasheet

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
46 of 101
Register Name:
RDULR
Register Description:
RCLK Disable Upon LOS Register
Register Address:
16h
Bit # 7 6 5 4 3 2 1 0
Name RDULR8 RDULR7 RDULR6 RDULR5 RDULR4 RDULR3 RDULR2 RDULR1
Default 0 0 0 0 0 0 0 0
Bits 7 to 0: RCLK Disable Upon LOS Register n (RDULRn). When this bit is set the RCLKn is disabled upon a
loss of signal and set as a low output. When reset, RCLKn switches to MCLK within 10ms of a loss of signal.
Register Name:
GISC
Register Description:
Global Interrupt Status Control Register
Register Address:
1Eh
Bit # 7 6 5 4 3 2 1 0
Name — — — — — — INTM CWE
Default 0 0 0 0 0 0 0 0
Bit 1: INT Pin Mode (INTM). This bit determines the inactive mode of the INTB pin. The INTB pin always drives low
when active.
0 = Pin is high impedance when not active.
1 = Pin drives high when not active.
Bit 0: Clear-On-Write Enable (CWE). When this bit is set, clear-on-write is enabled for all the latched interrupt
status registers. The host processor must write a 1 to the latched interrupt status register bit position before the
particular bit is cleared.