Datasheet

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
45 of 101
Register Name:
CCR
Register Description:
Clock Control Register
Register Address:
15h
Bit # 7 6 5 4 3 2 1 0
Name PCLKS2 PCLKS1 PCLKS0 TECLKS CLKA3 CLKA2 CLKA1 CLKA0
Default 0 0 0 0 0 0 0 0
Bits 7 to 5: PLL Clock Select (PCLKS[2:0]). These bits determine the RCLK that is to be used as the input to the
PLL. If an LOS is detected for the channel that RCLK is recovered from, the PLL switches to MCLK until the LOS is
cleared. When the LOS is cleared, the selected RCLK is used again. See
Table 5-15 for RCLK selection.
Table 5-15. PLL Clock Select
PCLKS[2:0]
PLL CLOCK
SELECTED
MC.PCLKI = 1
000 RCLK1
001 RCLK2
010 RCLK3
011 RCLK4
100 RCLK5
101 RCLK6
110 RCLK7
111 RCLK8
Bit 4: T1/E1 Clock Select (TECLKS). When this bit is set the T1/E1 clock output is 2.048MHz. When this bit is
reset the T1/E1 clock rate is 1.544MHz.
Bits 3 to 0: Clock A Select (CLKA[3:0]). These bits select the output frequency for CLKA pin. See
Table 5-16 for
available frequencies.
Table 5-16. Clock A Select
CLKA[3:0] MCLK (Hz)
0000 2.048M
0001 4.096M
0010 8.192M
0011 16.384M
0100 1.544M
0101 3.088M
0110 6.176M
0111 12.352M
1000 1.536M
1001 3.072M
1010 6.144M
1011 12.288M
1100 32k
1101 64k
1110 128k
1111 256k