Datasheet

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

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LVDS

Line Violation Detect Status Register

12h

Bit # 7 6 5 4 3 2 1 0

Name LVDS8

LVDS7 LVDS6 LVDS5 LVDS4 LVDS3 LVDS2 LVDS1

Default 0 0 0 0 0 0 0 0

Bits 7 to 0: Line Violation Detect Status n (LVDSn). A bipolar violation, code violation, or excessive zeros cause

the associated LVDSn bit to latch. This bit is cleared on a read operationif

GISC.CWE is reset. This bit is cleared

by a write operation to the bit if

GISC.CWE is set. The LVDS register captures the first violation within a three-

clock-period window. If a second violation occurs after the first violation within the three-clock-period window, then

the second violation will not be latched even if a read to the LVDS register was performed. Excessive zeros need to

be enabled by the

EZDE register for detection by this register. Code violations are only relative when in HDB3

mode and can be disabled for detection by this register by setting the

CVDEB register. In dual-rail mode only

bipolar violations are relevant for this register.

RCLKI

Receive Clock Invert Register

13h

Bit # 7 6 5 4 3 2 1 0

Name RCLKI8 RCLKI7 RCLKI6 RCLKI5 RCLKI4 RCLKI3 RCLKI2 RCLKI1

Default 0 0 0 0 0 0 0 0

Bits 7 to 0: Receive Clock Invert n (RCLKIn). When this bit is set the RCLKn is inverted. This aligns

RPOSn/RNEGn on the falling edge of RCLKn. When reset, RPOSn/RNEGn is aligned on the rising edge of

RCLKn. Note that if the CLKE pin is high, the RPOSn/RNEGn is set on the falling edge of RCLKn regardless of the

settings in this register.

TCLKI

Transmit Clock Invert Register

14h

Bit # 7 6 5 4 3 2 1 0

Name TCLKI8 TCLKI7 TCLKI6 TCLKI5 TCLKI4 TCLKI3 TCLKI2 TCLKI1

Default 0 0 0 0 0 0 0 0

Bits 7 to 0: Transmit Clock Invert n (TCLKIn). When this bit is set the TCLKn is inverted. TPOSn/TNEGn should

be aligned on the rising edge of TCLKn. When reset, TPOSn/TNEGn should be aligned on the falling edge of

TCLKn.