Datasheet

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

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Master Clock Select Register

06h

Bit # 7 6 5 4 3 2 1 0

Name — PCLKI TECLKE CLKAE MPS1 MPS0 FREQS PLLE

Default 0 0 0 0 0 0 0 0

Bit 6: PLL Clock Input (PCLKI). This bit selects the input into to the PLL.

0 = MCLK is used.

1 = RCLK[1:8] is used based on the selection in register

CCR.

Bit 5: T1/E1 Clock Enable (TECLKE). When this bit is set the TECLK output is enabled. If not set TECLK is

disabled and the TECLK output is an RLOS output. TECLK requires PLLE to be set for correct functionality.

Bit 4: Clock A Enable (CLKAE). When this bit is set the CLKA output is enabled. If not set, CLKA is disabled to tri-

state. CLKA requires PLLE to be set for correct functionality.

Bits 3 and 2: Master Period Select [1:0] (MPS[1:0]). These bits select the external MCLK frequency for the

DS26303. See

Table 5-13 for details.

Bit 1: Frequency Select (FREQS). In conjunction with MPS[1:0], this bit selects the external MCLK frequency for

the DS26303. If this bit is set, the external master clock can be 1.544MHz or a multiple thereof. If reset, the

external master clock can be 2.048MHz or a multiple thereof. See

Table 5-13 for details.

Bit 0: Phase Lock Loop Enable (PLLE). When this bit is set the phase lock loop is enabled. If reset, MCLK is the

applied input clock.

Table 5-13. MCLK Selections

PLLE MPS1, MPS0

MCLK

(MHz/±50ppm)

FREQS MODE

0 xx 1.544 x T1

0 xx 2.048 x E1

1 00 1.544 1 T1/J1 or E1

1 01 3.088 1 T1/J1 or E1

1 10 6.176 1 T1/J1 or E1

1 11 12.352 1 T1/J1 or E1

1 00 2.048 0 T1/J1 or E1

1 01 4.096 0 T1/J1 or E1

1 10 8.192 0 T1/J1 or E1

1 11 16.384 0 T1/J1 or E1