Datasheet

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

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5.1.3 Individual LIU Registers

IJAE

Individual Jitter Attenuator Enable Register

00h

Bit # 7 6 5 4 3 2 1 0

Name IJAE8 IJAE7 IJAE6 IJAE5 IJAE4 IJAE3 IJAE2 IJAE1

Default 0 0 0 0 0 0 0 0

Bits 7 to 0: Individual Jitter Attenuator Enable Channel n (IJAEn). When this bit is set, the LIUn jitter attenuator

is enabled. Note that if the

GC.JAE bit is set, this register is ignored.

IJAPS

Individual Jitter Attenuator Position Select Register

01h

Bit # 7 6 5 4 3 2 1 0

Name IJAPS8 IJAPS7 IJAPS6 IJAPS5 IJAPS4 IJAPS3 IJAPS2 IJAPS1

Default 0 0 0 0 0 0 0 0

Bits 7 to 0: Individual Jitter Attenuator Position Select Channel n (IJAPSn). When this bit is set , the jitter

attenuator is in the receive path of LIUn, and when this bit is reset the jitter attenuator is in the transmit path of

LIUn. Note that if the

GC.JAE bit is set, this register is ignored.

IJAFDS

Individual Jitter Attenuator FIFO Depth Select Register

02h

Bit # 7 6 5 4 3 2 1 0

Name IJAFDS8 IJAFDS7 IJAFDS6 IJAFDS5 IJAFDS4 IJAFDS3 IJAFDS2 IJAFDS1

Default 0 0 0 0 0 0 0 0

Bits 7 to 0: Individual Jitter Attenuator FIFO Depth Select n (IJAFDSn). When this bit is set for LIUn, the jitter

attenuator FIFO depth is 128 bits. When reset, the jitter attenuator FIFO depth is 32 bits. Note that if the

GC.IJAFDS bit is set, this register is ignored.

IJAFLT

Individual Jitter Attenuator FIFO Limit Trip Register

03h

Bit # 7 6 5 4 3 2 1 0

Name IJAFLT8

IJAFLT7 IJAFLT6 IJAFLT5 IJAFLT4 IJAFLT3 IJAFLT2 IJAFLT1

Default 0 0 0 0 0 0 0 0

Bits 7 to 0: Individual Jitter Attenuator FIFO Limit Trip n (IJAFLTn). Set when the jitter attenuator FIFO

reaches to within 4 bits of its useful limit for the transmitter of LIUn. This bit is cleared when read if

GISC.CWE is

reset. This bit is cleared by a write operation to the bit if

GISC.CWE is set.