Datasheet

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
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Register Name:
EZDE
Register Description:
Excessive Zero Detect Enable Register
Register Address:
05h
Bit # 7 6 5 4 3 2 1 0
Name EZDE8 EZDE7 EZDE6 EZDE5 EZDE4 EZDE3 EZDE2 EZDE1
Default 0 0 0 0 0 0 0 0
Bits 7 to 0: Excessive Zero Detect Enable Channel n (EZDEn). When this bit is reset, excessive zero detection
is disabled for LIUn. When this bit is set, excessive zero detect is enabled. Excessive zero detection is only
relevant in single-rail mode with HDB3 or B8ZS decoding.
Register Name:
CVDEB
Register Description:
Code Violation Detect Enable Bar Register
Register Address:
06h
Bit # 7 6 5 4 3 2 1 0
Name CVDEB8 CVDEB7 CVDEB6 CVDEB5 CVDEB4 CVDEB3 CVDEB2 CVDEB1
Default 0 0 0 0 0 0 0 0
Bits 7 to 0: Code Violation Detect Enable Bar Channel n (CVDEBn). If this bit is set, code violation detection is
disabled for the LIUn. If this bit is reset, code violation detection is enabled. Code violation detection is only
relevant with HDB3 decoding. Note that if the
GC.CODE bit is set, this register is ignored.