Datasheet

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
37 of 101
Register Name:
AISIE
Register Description:
AIS Interrupt Enable Register
Register Address:
14h
Bit # 7 6 5 4 3 2 1 0
Name AISIE8 AISIE7 AISIE6 AISIE5 AISIE4 AISIE3 AISIE2 AISIE1
Default 0 0 0 0 0 0 0 0
Bits 7 to 0: AIS Interrupt Mask Channel n (AISIEn). When this bit is set, interrupts can be generated for LIUn if
AIS status transitions.
Register Name:
AISIS
Register Description:
AIS Interrupt Status Register
Register Address:
15h
Bit # 7 6 5 4 3 2 1 0
Name AISIS8
AISIS7 AISIS6 AISIS5 AISIS4 AISIS3 AISIS2 AISIS1
Default 0 0 0 0 0 0 0 0
Bits 7 to 0: AIS Interrupt Channel n (AISISn). This bit is set when AIS transitions from a 0 to 1 or 1 to 0. The
interupt for LIUn is enabled in
AISIE. This bit when latched is cleared by a read operation to the register if
GISC.CWE is reset. This bit when latched is cleared by a write operation to the bit if GISC.CWE is set.
Register Name:
ADDP
Register Description:
Address Pointer for Bank Selection Register
Register Address:
1Fh
Bit # 7 6 5 4 3 2 1 0
Name ADDP7 ADDP6 ADDP5 ADDP4 ADDP3 ADDP2 ADDP1 ADDP0
Default 0 0 0 0 0 0 0 0
Bits 7 to 0: Address Pointer (ADDP). This pointer is used to switch between pointing to the primary registers, the
secondary registers, individual registers, and BERT registers. See
Table 5-12 for bank selection.
Table 5-12. Address Pointer for Bank Selection
ADDP[7:0] (HEX) BANK NAME
00 Primary Bank
AA Secondary Bank
01 Individual LIU Bank
02 BERT Bank