Datasheet

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

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ATAOS

Automatic Transmit All-Ones Select Register

0Eh

Bit # 7 6 5 4 3 2 1 0

Name ATAOS8 ATAOS7 ATAOS6 ATAOS5 ATAOS4 ATAOS3 ATAOS2 ATAOS1

Default 0 0 0 0 0 0 0 0

Bit 7 to 0: Automatic Transmit All-Ones Select Channel n (ATAOSn). When this bit is set an all-ones signal is

sent if a loss of signal is detected for LIUn. The all-ones signal uses MCLK as the reference clock.

Global Configuration Register

0Fh

Bit # 7 6 5 4 3 2 1 0

Name RIMPMS AISEL SCPD CODE JADS — JAPS JAE

Default 0 0 0 0 0 0 0 0

Bit 7: Receive Impedance Mode Select (RIMPMS). When this bit is set, the internal impedance mode is selected,

so all receive lines (RTIPn and RINGn) require no external resistance component. When this mode is selected, the

die-attach pad on the bottom of the package should be connected to ground for thermal dissipation. When reset,

external impedance mode is selected so all receive lines (RTIPn and RINGn) require external resistance. Note that

when in external impedance mode, if

TS.RIMPOFF is reset, the resistance is still adjusted internally for the T1

(100Ω), J1 (110Ω), and E1(75Ω) modes of operation by the template selected so that only one resistor value is

required externally. In E1 (120Ω), external impedance mode has no need for any internal adjustment.

Bit 6: AIS Enable During Loss (AISEL). When this bit is set, for all channels, an AIS is sent to the system side

upon detecting an LOS on the corresponding channel. The individual settings in the

IAISEL register are ignored

when this bit is set. When reset, the

IAISEL register has control.

Bit 5: Short-Circuit-Protection Disable (SCPD). If this bit is set, the short-circuit protection is disabled for all the

transmitters. The individual settings in

ISCPD are ignored when this bit is set. When reset, the ISCPD register has

control.

Bit 4: Code (CODE). If this bit is set, AMI encoding/decoding is selected. The individual settings in register

LCS

are ignored when this bit is set. If reset, the

LCS register has control.

Bit 3: Jitter Attenuator Depth Select (JADS). If this bit is set the jitter attenuator FIFO depth is 128 bits. The

individual settings in register

IJAFDS are ignored if this bit is set. If reset, the IJAFDS register has control.

Bit 1: Jitter Attenuator Position Select (JAPS). When the JAPS bit is set high, the jitter attenuator is in the

receive path, and when it is set low, it is in the transmit path. The individual settings in register

IJAPS are ignored if

this bit is set. If reset, the

IJAPS register has control.

Bit 0: Jitter Attenuator Enable (JAE). When this bit is set the jitter attenuator is enabled. The individual settings in

IJAE are ignored if this bit is set. If reset, the IJAE register has control.