Datasheet

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
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Table 5-2. Secondary Register Set
ADDRESS
REGISTER NAME
HEX
PARALLEL
INTERFACE
A[7:0] (HEX)
SERIAL
INTERFACE
A[7:1] (HEX)
RW
Single-Rail Mode Select SRMS 00 xxx00000 xx00000 RW
Line Code Selection LCS 01 xxx00001 xx00001 RW
Reserved — 02 xxx00010 xx00010 —
Receive Power-Down Enable RPDE 03 xxx00011 xx00011 RW
Transmit Power-Down Enable TPDE 04 xxx00100 xx00100 RW
Excessive Zero Detect Enable EZDE 05 xxx00101 xx00101 RW
Code Violation Detect Enable Bar CVDEB 06 xxx00110 xx00110 RW
Reserved — 07–1E
xxx00111–
xxx11110
xx00111–
xx11110
—
Address Pointer for Bank Selection ADDP 1F xxx11111 xx11111 RW
Table 5-3. Individual LIU Register Set
ADDRESS
REGISTER NAME
HEX
PARALLEL
INTERFACE
A[7:0] (HEX)
SERIAL
INTERFACE
A[7:1] (HEX)
RW
Individual Jitter Attenuator Enable IJAE 00 xxx00000 xx00000 RW
Individual Jitter Attenuator Position Select IJAPS 01 xxx00001 xx00001 RW
Individual Jitter Attenuator FIFO Depth Select IJAFDS 02 xxx00010 xx00010 RW
Individual Jitter Attenuator FIFO Limit Trip IJAFLT 03 xxx00011 xx00011 R
Individual Short Circuit Protection Disabled ISCPD 04 xxx00100 xx00100 RW
Individual AIS Select IAISEL 05 xxx00101 xx00101 RW
Master Clock Select MC 06 xxx00110 xx00110 RW
Global Management Register GMR 07 xxx00111 xx00111 RW
Reserved — 08–0B
xxx01000–
xxx01011
xx01000–
xx01011
RW
Reserved — 0C–0F
xxx01100–
xxx01111
xx01100–
xx01111
R
Bit Error Rate Tester Control BTCR 10 xxx10000 xx10000 RW
BPV Error Insertion BEIR 11 Xxx10001 xxx10001 RW
Line Violation Detect Status LVDS 12 xxx10010 xx10010 R
Receive Clock Invert RCLKI 13 xxx10011 xx10011 RW
Transmit Clock Invert TCLKI 14 xxx10100 xx10100 RW
Clock Control CCR 15 xxx10101 xx10101 RW
RCLK Disable Upon LOS RDULR 16 xxx10110 xx10110 RW
Global Interrupt Status Control GISC 1E xxx11110 xx11110 RW
Address Pointer for Bank Selection ADDP 1F xxx11111 xx11111 RW