Datasheet

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
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4.1.2 Serial Port Operation
Setting MODESEL = VDDIO/2 enables the serial bus interface on the DS26303. Port read/write timing is unrelated
to the system transmit and receive timing, allowing asynchronous reads or writes by the host. See Section
10.3 for
the AC timing of the serial port. All serial port accesses are LSB first. See
Figure 4-2 to Figure 4-4.
This port is compatible with the SPI interface defined for Motorola processors. An example of this is Motorola’s
MMC2107.
Reading or writing to the internal registers requires writing one address/command byte prior to transferring register
data. The first bit written (LSB) of the address/command byte specifies whether the access is a read (1) or a write
(0). The next 5 bits identify the register address (A1 to A5; A6 and A7 are ignored).
All data transfers are initiated by driving the CSB input low. When CLKE is low, SDO data is output on the rising
edge of SCLK and when CLKE is high, data is output on the falling edge of SCLK. Data is held until the next falling
or rising edge. All data transfers are terminated if CSB input transitions high. Port control logic is disabled and SDO
is tri-stated when CSB is high. SDI is always sampled on the rising edge of SCLK.
Figure 4-2. Serial Port Operation for Write Access
12345678910 111213141516SCLK
CSB
0
A1 A2 A3 A4 A5 A6 X
(msb)
SDI
SDO
D1 D2 D3 D4 D5 D7
(lsb) (msb)
DO D6
(lsb)
WRITE ACCESS ENABLED
Figure 4-3. Serial Port Operation for Read Access with CLKE = 0
12345678910111213141516
0
A1 A2 A3 A4 A5
D1 D2 D3 D4 D5 D6
SCLK
SDI
SDO
CSB
(lsb)
(msb)
D0
(lsb)
D7
(msb)
A6
X
Read
Access
Enabled