Datasheet

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
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4.1 Hardware and Host Port Operation
4.1.1 Hardware Mode
The DS26303 supports a hardware configuration mode that allows the user to configure the device through setting
levels on the device’s pins. This mode allows the configuration of the DS26303 without the use of a
microprocessor. Not all of the device features are supported in the hardware mode. To see all available options for
this hardware mode, see the pin descriptions in
Table 4-1.
Table 4-2 provides two basic examples of configurations available in hardware mode by setting pins.
Table 4-2. Hardware Mode Configuration Examples
STANDARD MODE CONFIGURATION
PIN NAME,
HARDWARE
MODE
T1 E1
NOTES
TTIP[8:1] Output Output
TRING[8:1] Output Output
RTIP[8:1] Input Input
RRING[8:1] Input Input
TPOS[8:1] Input Input
TNEG[8:1] Input Input
TCLK[8:1] Input: 1.544MHz Input: 2.048MHz
RPOS[8:1] Output Output
RNEG[8:1] Output Output
RCLK[8:1] Output: 1.544MHz Output: 2.048MHz
MCLK Input: 1.544MHz Input: 2.048MHz Used as recovery clock.
RLOS[8:1] Output Output Meets T1.231 and ITU-T G.775.
MODESEL 0 0 Low for hardware mode.
TIMPRM 0
0
(Part number ends in -75)
100Ω for T1 mode/75Ω E1 mode.
CODE 1 1 AMI encoding/decoding.
JAS N.C.: Pulled to V
DDIO
/2 N.C.: Pulled to V
DDIO
/2 Jitter attenuator is not used.
TS[2:0] 111 000
Set template T1 (655ft)-100Ω/E1-75Ω.
RIMPOFF 0 0
Receive impedance should default to
on.
INTB
N.C. N.C. Not used in hardware mode.
LP[8:1] N.C.: Pulled to V
DDIO
/2 N.C.: Pulled to V
DDIO
/2 Internally pulled to V
DDIO
/2.
RIMPMS 0 0 Internal impedance mode selected.
GMC[3:0] 0000 0000 No monitoring enabled.
OE 1 1
All TTIPn and TRINGn outputs are
enabled.
CLKE 0 0
RPOSn/RNEGn are clocked on rising
edge.
JTRSTB Input, Pulled Up Input, Pulled Up JTAG.
JTMS Input Input
JTCLK Input Input
JTDO Output, High-Z Output, High-Z
JTDI Input, Pulled Up Input, Pulled Up
RSTB Input, Pullup Input, Pullup Reset.
CLKA N.C. N.C. Not available in hardware node.
PIN 94 N.C. N.C.