Datasheet

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
17 of 101
NAME PIN TYPE FUNCTION
A4/RIMPMSB 12
A3/GMC3 13
A2/GMC2 14
A1/GMC1 15
A0/GMC0 16
I
Address Bus 4–0/G.772 Monitoring Control/Rx Impedance
Mode Select
A[4:0]: These five pins are address pins in parallel host mode. In
serial host mode and multiplexed host mode, these pins should be
grounded.
RIMPMSB: In hardware mode when this pin is low, the internal
impedance mode is selected, so all RTIP and RING pins require
no external resistance component. When high, external
impedance mode is selected so all RTIP and RING pins require
external resistance.
GMC[3:0]: In hardware mode, these signal pins are used to select
a transmit line (TTIPn/TRINGn) or receive line (RTIPn/RRINGn)
for nonintrusive monitoring. Receiver 1 is used to monitor
channels 2 to 8 See
Table 5-9.
OE 114 I
Output Enable. If this pin is pulled low, all the transmitter outputs
(TTIPn and TRINGn) are high impedance. Additionally, the user
may use this same pin to turn off all the impedance matching for
the receivers at the same time if register bit
GMR.RHPMC is set.
CLKE 115 I
Clock Edge. When CLKE is high, SDO is valid on the falling edge
of SCLK. When CLKE is low SDO is valid on the rising edge of
SCLK. When CLKE is high, the RCLKn for all the channels is
inverted. This aligns RPOSn/RNEGn on the falling edge of RCLKn
and overrides the settings in register
RCLKI. When low,
RPOSn/RNEGn is aligned according to the settings in register
RCLKI.
JTAG
JTRSTB 95 I, pullup
JTAG Test Port Reset. This pin if low resets the JTAG port. If not
used it can be left floating.
JTMS 96 I, pullup
JTAG Test Mode Select. This pin is clocked on the rising edge of
JTCLK and is used to control the JTAG selection between scan
and test machine control.
JTCLK 97 I
JTAG Test Clock. The data JTDI and JTMS are clocked on rising
edge of JTCLK and JTDO is clocked out on the falling edge of
JTCLK.
JTDO 98
O,
high-Z
JTAG Test Data Out. This is the serial output of the JTAG port.
The data is clocked out on the falling edge of JTCLK.
JTDI 99 I, pullup
Test Data Input. This pin input is the serial data of the JTAG test.
The data on JTDI is clocked on the rising edge of JTCLK. This pin
can be left unconnected.