Datasheet

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
13 of 101
NAME PIN TYPE FUNCTION
RNEG1/CV1 41
RNEG2/CV2 34
RNEG3/CV3 76
RNEG4/CV4 69
RNEG5/CV5 112
RNEG6/CV6 105
RNEG7/CV7 4
RNEG8/CV8 141
O,
tri-state
Receive Negative-Data Output for Channel 1 to 8/Code
Violation for Channel 1 to 8
RNEG[1:8]: In dual-rail mode, this output indicates a negative
pulse on RTIPn/RRINGn. If a given receiver is in power-down
mode, the corresponding RNEGn pin is high impedance.
CV[1:8]: In single-rail mode, bipolar violation, code violation, and
excessive zeros are reported by driving CVn high for one clock
cycle. If HDB3 or B8ZS encoding is not selected, this pin indicates
only BPVs.
Note: During an RLOS condition, the RNEGn/CVn output remains
active.
RCLK1 39
RCLK2 32
RCLK3 78
RCLK4 71
RCLK5 110
RCLK6 103
RCLK7 6
RCLK8 143
O,
tri-state
Receive Clock for Channel 1 to 8. The receive data
RPOSn/RNEGn or RDATn is clocked out on the rising edge of
RCLKn. RCLKn can be inverted. If a given receiver is in power-
down mode, RCLKn is high impedance.
MCLK 10 I
Master Clock. This is an independent free-running clock that can
be a multiple of 2.048MHz ±50ppm for E1 mode or 1.544MHz
±50ppm for T1 mode. The clock selection is available by
MC bits
MPS0, MPS1, FREQS, and PLLE. A multiple of 2.048MHz can be
internally adapted to 1.544MHz and a multiple of 1.544MHz can
be internally adapted to 2.048MHz. In hardware mode, internal
adaptation is not available so the user must provide 2.048MHz
±50ppm for E1 mode or 1.544MHz ±50ppm for T1 mode.
RLOS1/TECLK 42 O
Loss-of-Signal Output/T1-E1 Clock
RLOS1: This output goes high when there are no transitions on
the receiveline over a specified interval. The output goes low when
there is sufficient ones density on the receiveline. The RLOS
assertion and desertion criteria are described in the Functional
Description section. The RLOS outputs can be configured to
comply with T1.231, ITU-T G.775, or ETS 300 233. In hardware
mode, ETS 300 233 “RLOS Criteria” is not available.
TECLK: When enabled (
MC.TECLKE is set), this output becomes
a T1- or E1-programmable clock output. For T1 or E1 frequency
selection, see the
CCR register. This option is not available in
hardware mode.
RLOS2 35
RLOS3 75
RLOS4 68
RLOS5 113
RLOS6 106
RLOS7 3
RLOS8 140
O
Loss-of-Signal Output
RLOS[2:8]: RLOS2: This output goes high when there are no
transitions on the receiveline over a specified interval. The output
goes low when there is sufficient ones density on the receiveline.
The RLOS assertion and desertion criteria are described in the
Functional Description (Section
6). The RLOS outputs can be
configured to comply with T1.231, ITU-T G.775, or ETS 300 233.
In hardware mode, ETS 300 233 “RLOS Criteria” is not available.