Datasheet

1-Wire 4Kb EEPROM
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= -40°C to +85°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IO PIN: 1-Wire WRITE
Standard speed 60 120
Write-Zero Low Time
(Notes 2, 16)
t
W0L
Overdrive speed 6 16
µs
Standard speed 5 15
Write-One Low Time
(Notes 2, 16)
t
W1L
Overdrive speed 1 2
µs
IO PIN: 1-Wire READ
Standard speed 5 15 - 
Read Low Time
(Notes 2, 17)
t
RL
Overdrive speed 1 2 - 
µs
Standard speed t
RL
+  15
Read Sample Time
(Notes 2, 17)
t
MSR
Overdrive speed t
RL
+  2
µs
EEPROM
Programming Current I
PROG
(Note 18) 2 mA
Programming Time t
PROG
(Note 19) 5 ms
At +25°C 200,000
Write/Erase Cycles (Endurance)
(Notes 20, 21)
N
CY
At +85°C (worst case) 50,000
—
Data Retention (Notes 22, 23, 24) t
DR
At +85°C (worst case) 40 Years
Note 1: Limits are 100% production tested at T
A
= +25°C and/or T
A
= +85°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2: System requirement.
Note 3: When operating near the minimum operating voltage (2.8V), a falling edge slew rate of 15V/µs or faster is recommended.
Note 4: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system, 1-Wire recovery times,
and current requirements during EEPROM programming. The specified value here applies to systems with only one
device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found
in the DS2482-x00 or DS2480B may be required.
Note 5: Capacitance on the data pin could be 2500pF when V
PUP
is first applied. Once the parasite capacitance is charged, it
does not affect normal communication.
Note 6: Guaranteed by design, characterization, and/or simulation only. Not production tested.
Note 7: V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage, which is a function of V
PUP
, R
PUP
, 1-Wire timing, and
capacitive loading on IO. Lower V
PUP
, higher R
PUP
, shorter t
REC
, and heavier capacitive loading all lead to lower values of
V
TL
, V
TH
, and V
HY
.
Note 8: Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 9: The voltage on IO must be less than or equal to V
ILMAX
at all times while the master is driving IO to a logic 0 level.
Note 10: Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 11: After V
TH
is crossed during a rising edge on IO, the voltage on IO must drop by at least V
HY
to be detected as logic 0.
Note 12: The I-V characteristic is linear for voltages less than +1V.
Note 13: Applies to a single DS24B33 attached to a 1-Wire line.
Note 14: Defines maximum possible bit rate. Equal to 1/(t
W0LMIN
+ t
RECMIN
).
Note 15: Interval after t
RSTL
during which a bus master can read a logic 0 on IO if there is a DS24B33 present. The power-up presence
detect pulse could be outside this interval but will be complete within 2ms after power-up.
Note 16: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to V
TH
. The actual
maximum duration for the master to pull the line low is t
W1LMAX
+ t
F
- ε and t
W0LMAX
+ t
F
- ε, respectively.
Note 17: δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input high
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
RLMAX
+ t
F
.
Note 18: Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO should be such that during the
programming interval, the voltage at IO is greater than or equal to V
PUPMIN
. If V
PUP
in the system is close to V
PUPMIN
, then
a low-impedance bypass of R
PUP
, which can be activated during programming, may need to be added.
Maxim Integrated
3
DS24B33