Datasheet

9Maxim Integrated
DS2483
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
Status Register
The read-only Status register is the general means for
the DS2483 to report bit-type data from the 1-Wire side,
1-Wire busy status, and its own reset status to the host
processor (Table 3). All 1-Wire communication com-
mands and the Device Reset command position the read
pointer at the Status register for the host processor to
read with minimal protocol overhead. Status information
is updated during the execution of certain commands
only. Bit details are given in the following descriptions.
1-Wire Busy (1WB)
The 1WB bit reports to the host processor whether the
1-Wire line is busy. During 1-Wire communication 1WB
is 1; once the command is completed, 1WB returns to
its default 0. Details on when 1WB changes state and
for how long it remains at 1 are found in the Function
Commands section.
Presence-Pulse Detect (PPD)
The PPD bit is updated with every 1-Wire Reset com-
mand. If the DS2483 detects a presence pulse from a
1-Wire device at t
MSP
during the presence-detect cycle,
the PPD bit is set to 1. This bit returns to its default 0 if
there is no presence pulse or if the 1-Wire line is shorted
during a subsequent 1-Wire Reset command.
Short Detected (SD)
The SD bit is updated with every 1-Wire Reset com-
mand. If the DS2483 detects a logic 0 on the 1-Wire line
at t
SI
during the presence-detect cycle, the SD bit is set
to 1. This bit returns to its default 0 with a subsequent
1-Wire Reset command, provided that the short has been
removed. If SD is 1, PPD is 0. The DS2483 cannot dis-
tinguish between a short and a DS1994 or DS2404 sig-
naling a 1-Wire interrupt. For this reason, if a DS2404 or
DS1994 is used in the application, the interrupt function
must be disabled. The interrupt signaling is explained in
the respective Maxim 1-Wire IC data sheets.
Logic Level (LL)
The LL bit reports the logic state of the active 1-Wire line
without initiating any 1-Wire communication. The 1-Wire
line is sampled for this purpose every time the Status
register is read. The sampling and updating of the LL bit
takes place when the host processor has addressed the
DS2483 in read mode (during the acknowledge cycle),
provided that the read pointer is positioned at the Status
register.
Device Reset (RST)
If the RST bit is 1, the DS2483 has performed an internal
reset cycle, either caused by a power-on reset or from
executing the Device Reset command. The RST bit is
cleared automatically when the DS2483 executes a Write
Device Configuration command to restore the selection
of the desired 1-Wire features.
Single Bit Result (SBR)
The SBR bit reports the logic state of the active 1-Wire
line sampled at t
MSR
of a 1-Wire Single Bit command or
the first bit of a 1-Wire Triplet command. The power-on
default of SBR is 0. If the 1-Wire Single Bit command
sends a 0 bit, SBR should be 0. With a 1-Wire Triplet
command, SBR could be 0 as well as 1, depending on
the response of the 1-Wire devices connected. The same
result applies to a 1-Wire Single Bit command that sends
a 1 bit.
Triplet Second Bit (TSB)
The TSB bit reports the logic state of the active 1-Wire
line sampled at t
MSR
of the second bit of a 1-Wire Triplet
command. The power-on default of TSB is 0. This bit is
updated only with a 1-Wire Triplet command and has no
function with other commands.
Branch Direction Taken (DIR)
Whenever a 1-Wire Triplet command is executed, this bit
reports to the host processor the search direction that
was chosen by the third bit of the triplet. The power-on
default of DIR is 0. This bit is updated only with a 1-Wire
Triplet command and has no function with other com-
mands. For additional information, see the description of
the 1-Wire Triplet command and Application Note 187:
1-Wire Search Algorithm.
Table 3. Status Register Bit Assignment
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DIR TSB SBR RST LL SD PPD 1WB