Datasheet

6Maxim Integrated
DS2483
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
Detailed Description
The DS2483 is a self-timed 1-Wire master that supports
advanced 1-Wire waveform features including standard
and overdrive speeds, active pullup, and strong pullup
for power delivery. The active pullup affects rising edges
on the 1-Wire side. The strong pullup function uses the
same pullup transistor as the active pullup, but with a
different control algorithm. Once supplied with command
and data, the input/output controller of the DS2483 per-
forms time-critical 1-Wire communication functions such
as reset/presence-detect cycle, read-byte, write-byte,
single bit R/W, and triplet for ROM Search, without requir-
ing interaction with the host processor. The host obtains
feedback (completion of a 1-Wire function, presence
pulse, 1-Wire short, search direction taken) through the
Status register and data through the Read Data regis-
ter. The DS2483 communicates with a host processor
through its I
2
C bus interface in standard mode or in fast
mode. See Figure 1 for a block diagram.
Device Registers
The DS2483 has four registers that the I
2
C host can
read: Device Configuration, Status, Read Data, and Port
Configuration. These registers are addressed by a read
pointer. The position of the read pointer, i.e., the reg-
ister that the host reads in a subsequent read access,
is defined by the instruction the DS2483 executed last.
To enable certain 1-Wire features, the host has read-
and write-access to the Device Configuration and Port
Configuration registers.
Device Configuration Register
The DS2483 supports four 1-Wire features that are
enabled or selected through the Device Configuration
register (Table 1). These features are as follows:
• ActivePullup(APU)
• 1-WirePower-Down(PDN)
• StrongPullup(SPU)
• 1-WireSpeed(1WS)
APU, SPU, and 1WS can be selected in any combination.
While APU and 1WS maintain their states, SPU returns to
its inactive state as soon as the strong pullup has ended.
After a device reset (power-up cycle or initiated by the
Device Reset command), the Device Configuration reg-
ister reads 00h. When writing to the Device Configuration
register, the new data is accepted only if the upper nibble
(bits 7 to 4) is the one’s complement of the lower nibble
(bits 3 to 0). When read, the upper nibble is always 0h.
Figure 1. Block Diagram
Table 1. Device Configuration Register Bit Assignment
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
1WS SPU PDN APU
1WS SPU PDN APU
CONFIGURATION AND
TIMING REGISTER
I
2
C
INTERFACE
CONTROLLER
INPUT/OUTPUT
CONTROLLER
LINE
XCVR
T-TIME OSC
STATUS
REGISTER
READ DATA
REGISTER
SDA
IO
SLPZ
GND
SCL
V
CC
DS2483