Datasheet

4Maxim Integrated
DS2483
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
Note 1: Limits are 100% production tested at T
A
= +25°C and/or T
A
= +85°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2: The V
CI2C
voltage is applied at the SLPZ pin. V
CI2C
must always be < V
CC
. The DS2483 measures V
CI2C
after t
SWUP
(wakeup from sleep mode) or after t
OSCWUP
(power-on reset). The Device Reset command does not cause the DS2483 to
measure V
CI2C
.
Note 3: The active pullup does not apply to the rising edge of a presence pulse outside of a 1-Wire Reset command or during the
recovery after a short on the 1-Wire line.
Note 4: Guaranteed design and not production tested.
Note 5: Except for t
F1
, all 1-Wire timing specifications are derived from the same timing circuit.
Note 6: Although 1-Wire slave data sheets specify a t
W1L
and t
RL
minimum of 1µs, 1-Wire slaves will accept the shorter 0.71µs
t
W1L
and t
RL
of the DS2483.
Note 7: V
CCACT
refers to the V
CC
level being applied in the application.
Note 8: I
2
C communication should not take place for the max t
OSCWUP
or t
SWUP
time following a power-on reset or a wake-up
from sleep mode.
Note 9: All I
2
C timing values are referenced to V
IH(MIN)
and V
IL(MAX)
levels.
Note 10: The DS2483 does not obstruct the SDA and SCL lines if SLPZ is at 0V or if V
CC
is switched off.
Note 11: The DS2483 provides a hold time of at least 300ns for the SDA signal (referenced to the V
IH(MIN)
of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 12: The maximum t
HD:DAT
must only be met if the device does not stretch the low period (t
LOW
) of the SCL signal.
Note 13: A fast mode I
2
C bus device can be used in a standard mode I
2
C bus system, but the requirement t
SU:DAT
R 250ns
must then be met. This requirement is met since the DS2483 does not stretch the low period of the SCL signal. Also the
acknowledge timing must meet this setup time (I
2
C bus specification Rev. 03, 19 June 2007).
Note 14: C
B
= Total capacitance of one bus line in pF. The maximum bus capacitance allowable can vary from this value depend-
ing on the actual operating voltage and frequency of the application (I
2
C bus specification Rev. 03, 19 June 2007).
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Current with Input Voltage
Between 0.1 O V
CC(MAX)
and 0.9
O V
CC(MAX)
I
I
(Note 10) -10 +10
FA
Input Capacitance C
I
(Note 4) 10 pF
SCL Clock Frequency f
SCL
0 400 kHz
Hold Time (Repeated) START
Condition (After this period, the
first clock pulse is generated.)
t
HD:STA
0.6
Fs
Low Period of the SCL Clock t
LOW
1.3
Fs
High Period of the SCL Clock t
HIGH
0.6
Fs
Setup Time for a Repeated
START Condition
t
SU:STA
0.6
Fs
Data Hold Time t
HD:DAT
(Notes 11, 12) 0.9
Fs
Data Setup Time t
SU:DAT
(Note 13) 250 ns
Setup Time for STOP Condition t
SU:STO
0.6
Fs
Bus Free Time Between a STOP
and START Condition
t
BUF
1.3
Fs
Capacitive Load for Each Bus
Line
C
B
(Notes 4, 14) 400 pF
Oscillator Warmup Time t
OSCWUP
(Notes 4, 8) 2 ms