Datasheet

Maxim Integrated | 11www.maximintegrated.com
DS2482-100
Single-Channel 1-Wire Master
PULLUP DS2482-100 PULLDOWN 1-Wire SLAVE PULLDOWN
V
CC
V
IH1
V
IL1
0V
RESET PULSE
RESISTIVE PULLUP
PRESENCE PULSE
APU CONTROLLED
EDGE
PRESENCE/SHORT DETECT
t
RSTL
t
SI
t
MSP
t
RSTH
t
F1
Figure 4. 1-Wire Reset/Presence-Detect Cycle
1-Wire Single Bit
Command Code 87h
Command Parameter Bit Byte
Description
Generates a single 1-Wire time slot with a bit value “V” as specified by the bit byte at the 1-Wire
line (see Table 2). A V value of 0b generates a write-zero time slot (Figure 5); a V value of 1b
generates a write-one time slot, which also functions as a read-data time slot (Figure 6). In either
case, the logic level at the 1-Wire line is tested at t
MSR
and SBR is updated.
Typical Use
To perform single-bit writes or reads at the 1-Wire line when single bit communication is
necessary (the exception).
Restriction 1-Wire activity must have ended before the DS2482-100 can process this command.
Error Response
Command code and bit byte are not acknowledged if 1WB = 1 at the time the command code is
received and the command is ignored.
Command Duration t
SLOT
+ maximum 262.5ns, counted from the falling SCL edge of the first bit (MSB) of the bit byte.
1-Wire Activity Begins maximum 262.5ns after the falling SCL edge of the MSB of the bit byte.
Read Pointer Position Status Register (for busy polling and data reading).
Status Bits Affected 1WB (set to 1 for t
SLOT
), SBR is updated at t
MSR
, DIR (may change its state).
Configuration Bits Affected 1WS, APU, SPU apply.
Table 2. Bit Allocation in the Bit Byte
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
V x x x x x x x
x = Don’t care.