Datasheet

6Maxim Integrated
DS2465
DeepCover Secure Authenticator with
SHA-256 Coprocessor and 1-Wire Master Function
ABRIDGED DATA SHEET
Memory
Figure 2 shows the memory organization of the DS2465.
The memory begins at address 00h with the input
scratchpad. The register section follows at address 60h.
Addresses 00 to 6F
are implemented as
volatile SRAM. The 1-Wire port configuration settings
have default values that are loaded automatically during
power-on. The address range 70h and higher is non-
volatile. It contains factory-programmed device identi-
fication data, a personality byte, and the user memory
pages.
Refer to the full data sheet for this information.
Figure 1. Block Diagram
1-Wire MASTER
STATUS REGISTER
1-WIRE READ
DATA REGISTER
IO
CONTROLLER
LINE
TRANSCEIVER
IO
SDA
SCL
SLPZ
GND
USER EEPROM
PAGES
SCRATCHPAD
T-TIME OSCILLATOR
Refer to the full data sheet for this
information.
Refer to the full
data sheet.
I
2
C
INTERFACE
CONTROLLER
1-Wire PORT
CONFIGURATION
AND TIMING
REGISTERS
V
CC
DS2465