Datasheet

4Maxim Integrated
DS2465
DeepCover Secure Authenticator with
SHA-256 Coprocessor and 1-Wire Master Function
ABRIDGED DATA SHEET
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= -40NC to +85NC, unless otherwise noted.) (Note 1)
Note 1: Limits are 100% production tested at T
A
= +25°C and/or T
A
= +85°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2: Operating current with 1-Wire write byte sequence followed by continuous read of 1-Wire Master Status register at 400kHz
in overdrive.
Note 3: Guaranteed by design and/or characterization only. Not production tested.
Note 4: Active pullup or resistive pullup and range are configurable.
Note 5: The active pullup does not apply to the rising edge of a presence pulse outside of a 1-Wire Reset Pulse command or
during the recovery after a short on the 1-Wire line.
Note 6: All 1-Wire timing specifications are derived from the same timing circuit.
Note 7: Current drawn from V
CC
during the EEPROM programming interval or SHA-256 computation.
Note 8: Write-cycle endurance is tested in compliance with JESD47G.
Note 9: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 10: Data retention is tested in compliance with JESD47G.
Note 11: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 12: I
2
C communication should not take place for the max t
OSCWUP
or t
SWUP
time following a power-on reset or a wake-up
from sleep mode.
Note 13: All I
2
C timing values are referred to V
IH(MIN)
and V
IL(MAX)
levels.
Note 14: I/O pins of the DS2465 do not obstruct the SDA and SCL lines if V
CC
is switched off.
Note 15: The DS2465 provides a hold time of at least 300ns for the SDA signal (referenced to the V
IH(MIN)
of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 16: The maximum t
HD:DAT
has only to be met if the device does not stretch the low period (t
LOW
) of the SCL signal. If the
clock stretches the SCL, the data must be valid by the setup time before it releases the clock (I
2
C bus specification
Rev. 03, 19 June 2007).
Note 17: A fast-mode I
2
C bus device can be used in a standard-mode I
2
C-bus system, but the requirement t
SU:DAT
R 250ns must
then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device
does stretch the low period of the SCL signal, it must output the next data bit to the SDA line t
R(MAX)
+ t
SU:DAT
= 1000 +
250 = 1250ns (according to the standard-mode I
2
C bus specification) before the SCL line is released. Also the acknowl-
edge timing must meet this setup time (I
2
C bus specification Rev. 03, 19 June 2007).
Note 18: C
B
= Total capacitance of one bus line in pF. The maximum bus capacitance allowable may vary from this value depend-
ing on the actual operating voltage and frequency of the application (I
2
C bus specification Rev. 03, 19 June 2007).
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Capacitance C
I
(Note 3) 10 pF
SCL Clock Frequency f
SCL
0 400 kHz
Hold Time (Repeated) START
Condition; After this Period, the
First Clock Pulse is Generated
t
HD:STA
(Note 3) 0.6
Fs
Low Period of the SCL Clock t
LOW
(Note 3) 1.3
Fs
High Period of the SCL Clock t
HIGH
(Note 3) 0.6
Fs
Setup Time for a Repeated
START Condition
t
SU:STA
(Note 3) 0.6
Fs
Data Hold Time t
HD:DAT
(Notes 3, 15, 16) 0.9
Fs
Data Setup Time t
SU:DAT
(Notes 3, 17) 250 ns
Setup Time for STOP Condition t
SU:STO
(Note 3) 0.6
Fs
Bus Free Time Between a STOP
and START Condition
t
BUF
(Note 3) 1.3
Fs
Capacitive Load for Each Bus Line C
B
(Notes 3, 18) 400 pF
Oscillator Warmup Time t
OSCWUP
(Note 12) 200
Fs