Datasheet

35Maxim Integrated
DS2465
DeepCover Secure Authenticator with
SHA-256 Coprocessor and 1-Wire Master Function
ABRIDGED DATA SHEET
Repeated START Condition: Repeated STARTs are
commonly used for read accesses after having speci-
fied a memory address to read from in a preceding
write access. The master can use a repeated START
condition at the end of a data transfer to immediately
initiate a new data transfer following the current one. A
repeated START condition is generated the same way
as a normal START condition, but without leaving the
bus idle after a STOP condition.
Data Valid: With the exception of the START and STOP
condition, transitions of SDA can occur only during the
low state of SCL. The data on SDA must remain valid
and unchanged during the entire high pulse of SCL
plus the required setup and hold time (t
HD:DAT
after
the falling edge of SCL and t
SU:DAT
before the rising
edge of SCL; see Figure 10). There is one clock pulse
per bit of data. Data is shifted into the receiving device
during the rising edge of the SCL pulse.
When finished with writing, the master must release the
SDA line for a sufficient amount of setup time (minimum
t
SU:DAT
+ t
R
in Figure 10) before the next rising edge
of SCL to start reading. The slave shifts out each data
bit on SDA at the falling edge of the previous SCL pulse
and the data bit is valid at the rising edge of the current
SCL pulse. The master generates all SCL clock pulses,
including those needed to read from a slave.
Acknowledged by Slave: A slave device, when
addressed, is usually obliged to generate an acknowl-
edge after the receipt of each byte. The master must
generate the clock pulse for each acknowledge bit. A
slave that acknowledges must pull down the SDA line
during the acknowledge clock pulse so that it remains
stable low during the high period of this clock pulse.
Setup and hold times t
SU:DAT
and t
HD:DAT
must be
taken into account.
Acknowledged by Master: To continue reading from
a slave, the master is obliged to generate an acknowl-
edge after the receipt of each byte. The master must
generate the clock pulse for each acknowledge bit. A
master that acknowledges must pull down the SDA line
during the acknowledge clock pulse so that it remains
stable low during the high period of this clock pulse.
Setup and hold times t
SU:DAT
before the rising edge of
SCL and t
HD:DAT
after the falling edge of SCL must be
taken into account.
Not Acknowledged by Slave: A slave device may
be unable to receive or transmit data, for example,
because it is busy performing a real-time function such
as MAC computation or EEPROM write cycle or is in
sleep mode. In this case, the slave does not acknowl-
edge its slave address and leaves the SDA line high.
A slave that is ready to communicate acknowledges at
least its slave address. However, some time later the
Figure 10. I
2
C Timing Diagram
SCL
NOTE: TIMING IS REFERENCED TO V
IL(MAX)
AND V
IH(MIN)
.
SDA
STOP START REPEATED
START
SPIKE
SUPPRESSION
t
BUF
t
HD:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
HD:STA
t
SP
t
SU:STA
t
HIGH
t
R
t
F
t
LOW