Datasheet

11Maxim Integrated
DS2465
DeepCover Secure Authenticator with
SHA-256 Coprocessor and 1-Wire Master Function
ABRIDGED DATA SHEET
Bit 1: 1-Wire Power-Down (PDN). The PDN bit is used to remove power from the 1-Wire port, e.g., to force a 1-Wire
slave to perform a power-on reset. PDN interacts with the sleep mode, which is controlled by the SLPZ pin (Table 4).
The default state of PDN is 0, enabling normal operation. When PDN is changed to 1, no 1-Wire communication is
possible. To end the 1-Wire power-down state, the PDN bit needs to be changed to 0. To exit the DS2465 from sleep
mode, change the SLPZ pin state from 0 to 1. This forces the DS2465 to perform a power-on reset and clears PDN to
0 for normal operation.
Bit 0: Active Pullup (APU). The APU bit controls whether an active pullup (low impedance transistor) or a passive
pullup (R
WPU
resistor) is used to drive a 1-Wire line from low to high. When APU = 0, active pullup is disabled (resistor
mode). Enabling active pullup is generally recommended for best 1-Wire performance. The active pullup does not apply
to the rising edge of a recovery after a short on the 1-Wire line. If enabled, a fixed-duration active pullup (nominally
2.5Fs standard speed, 0.5Fs overdrive speed) also applies in a reset/presence detect cycle on the rising edges after
t
RSTL
and after t
PDL
.
The circuit that controls rising edges (Figure 4) operates as follows: At t
1
, the pulldown (from DS2465 or 1-Wire slave)
ends. From this point on the 1-Wire line is pulled high through R
WPU
internal to the DS2465. V
CC
and the capacitive load
of the 1-Wire line determine the slope. In case that active pullup is disabled (APU = 0), the resistive pullup continues,
as represented by the solid line. With active pullup enabled (APU = 1), and when at t
2
the voltage has reached the
V
IAPO
threshold, the DS2465 activates a low-impedance pullup transistor, as represented by the dashed line. The active
pullup remains active until the end of the time slot (t
3
), after which the resistive pullup continues. The shortest duration
of the active pullup is t
REC0
in a write-zero time slot and the longest duration is t
W0L
+ t
REC0
- t
W1L
in a write-one time
slot. In a read data time slot, the active pullup duration is slave dependent. See the strong pullup (SPU) section for a
way to keep the pullup transistor conducting beyond t
3
.
Figure 3. Low-Impedance Pullup Timing
Table 4. Interaction of PDN and SLPZ
SLPZ PIN IS AT LOGIC 0 SLPZ PIN IS AT LOGIC 1
PDN is 0
• R
WPU
is disconnected;
IO is at 0V, causing the slaves to lose power.
• The DS2465 is powered down (sleep mode).
• R
WPU
is connected;
IO is at V
CC
, keeping the slaves powered.
• The DS2465 is powered up (normal operation).
PDN is 1
• R
WPU
is disconnected;
IO is at 0V, causing the slaves to lose power.
• The DS2465 is powered up.
DS2465 RESISTIVE PULLUP DS2465 PULLDOWN DS2465 STRONG PULLUP
V
CC
V
IAPO
0V
WRITE-ZERO CASE
WRITE-ONE CASE
t
SLOT
LAST BIT OF 1-Wire WRITE BYTE, 1-Wire READ BYTE, OR 1-Wire SINGLE BIT FUNCTION
NEXT
TIME SLOT