Datasheet

DS2438
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SAMPLE COMMAND SEQUENCE Table 14
Example: Assuming a single DS2438 is configured for its current accumulators to function, this sequence
allows the Bus Master to read the three current accumulators.
MASTER MODE DATA (LSB FIRST) COMMENTS
TX Reset Reset pulse
RX Presence Presence pulse
TX CCh Skip ROM
TX B8h01h Issue Recall Memory page 01h command
TX Reset Reset pulse
RX Presence Presence pulse
TX CCh Skip ROM
TX BEh01h Issue Read SP 01h command
RX <9 data bytes> Read scratchpad data and CRC. The ICA is
located in byte 04h
TX Reset Reset pulse
RX Presence Presence pulse
TX CCh Skip ROM
TX B8h07h Issue Recall Memory page 07h command
TX Reset Reset pulse
RX Presence Presence pulse
TX CCh Skip ROM
TX B8h07h Issue Read SP 07h command
RX <9 data bytes> Read scratchpad data and CRC. The CCA is
located in bytes 04h-05h and the DCA is located in
bytes 06h-07h.
TX Reset Reset pulse
RX Presence Presence pulse, done
I/O SIGNALING
The DS2438 requires strict protocols to insure data integrity. The protocol consists of several types of
signaling on one line: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. All of these signals,
with the exception of the presence pulse, are initiated by the bus master.
The initialization sequence required to begin any communication with the DS2438 is shown in Figure 9.
A reset pulse followed by a presence pulse indicates the DS2438 is ready to send or receive data given the
correct ROM command and memory function command. The bus master transmits (Tx) a reset pulse (a
low signal for a minimum of 480 ms). The bus master then releases the line and goes into a receive
mode(Rx). The 1-Wire bus is pulled to a high state via the 5 kW pull-up resistor. After detecting the
rising edge on the I/O pin, the DS2438 waits 15-60 ms and then transmits the presence pulse (a low signal
for 60-240 ms). DS2438 data is read and written through the use of time slots to manipulate bits and a
command word to specify the transaction.