Datasheet
DS2431-A1
1024-Bit, 1-Wire EEPROM
for Automotive Applications
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Note 1: Specifications at T
A
= -40°C are guaranteed by design only and not production tested.
Note 2: System requirement.
Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.
The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more
heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Note 4: Maximum value represents the internal parasite capacitance when V
PUP
is first applied. If a 2.2kΩ resistor is used to pull
up the data line, 2.5µs after V
PUP
has been applied, the parasite capacitance does not affect normal communications.
Note 5: Guaranteed by design, characterization, and/or simulation only. Not production tested.
Note 6: V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage, which is a function of V
PUP
, R
PUP
, 1-Wire timing, and
capacitive loading on I/O. Lower V
PUP
, higher R
PUP
, shorter t
REC
, and heavier capacitive loading all lead to lower values
of V
TL
, V
TH
, and V
HY
.
Note 7: Voltage below which, during a falling edge on I/O, a logic 0 is detected.
Note 8: The voltage on I/O needs to be less than or equal to V
ILMAX
at all times the master is driving I/O to a logic-0 level.
Note 9: Voltage above which, during a rising edge on I/O, a logic 1 is detected.
Note 10: After V
TH
is crossed during a rising edge on I/O, the voltage on I/O must drop by at least V
HY
to be detected as logic 0.
Note 11: The I-V characteristic is linear for voltages less than 1V.
Note 12: Applies to a single device attached to a 1-Wire line.
Note 13: The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been reached on the preceding rising edge.
Note 14: Defines maximum possible bit rate. Equal to t
W0LMIN
+ t
RECMIN
.
Note 15: Interval after t
RSTL
during which a bus master is guaranteed to sample a logic 0 on I/O if there is a DS2431-A1 present.
Minimum limit is t
PDHMAX
; maximum limit is t
PDHMIN
+ t
PDLMIN
.
Note 16: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V
IL
to V
TH
. The actual
maximum duration for the master to pull the line low is t
W1LMAX
+ t
F
- ε and t
W0LMAX
+ t
F
- ε, respectively.
Note 17: δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V
IL
to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
RLMAX
+ t
F
.
Note 18: Current drawn from I/O during the EEPROM programming interval. The pullup circuit on I/O during the programming inter-
val should be such that the voltage at I/O is greater than or equal to V
PUPMIN
. If V
PUP
in the system is close to V
PUPMIN
, a
low-impedance bypass of R
PUP
, which can be activated during programming, may need to be added.
Note 19: Interval begins t
REHMAX
after the trailing rising edge on I/O for the last time slot of the E/S byte for a valid Copy
Scratchpad sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the cur-
rent drawn by the device has returned from I
PROG
to I
L
.
Note 20: Write-cycle endurance is degraded as T
A
increases.
Note 21: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 22: Data retention is degraded as T
A
increases.
Note 23: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 24: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-
peratures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.