Datasheet

DS2431-A1
1024-Bit, 1-Wire EEPROM
for Automotive Applications
______________________________________________________________________________________ 15
Slave-to-Master
A read-data time slot begins like a write-one time slot.
The voltage on the data line must remain below V
TL
until the read low time t
RL
is expired. During the t
RL
window, when responding with a 0, the DS2431-A1
starts pulling the data line low; its internal timing gener-
ator determines when this pulldown ends and the volt-
age starts rising again. When responding with a 1, the
DS2431-A1 does not hold the data line low at all, and
the voltage starts rising as soon as t
RL
is over.
The sum of t
RL
+ δ (rise time) on one side and the inter-
nal timing generator of the DS2431-A1 on the other side
define the master sampling window (t
MSRMIN
to
t
MSRMAX
), in which the master must perform a read from
the data line. For the most reliable communication, t
RL
should be as short as permissible, and the master
should read close to but no later than t
MSRMAX
. After
reading from the data line, the master must wait until
t
SLOT
is expired. This guarantees sufficient recovery time
t
REC
for the DS2431-A1 to get ready for the next time
slot. Note that t
REC
specified herein applies only to a sin-
gle DS2431-A1 attached to a 1-Wire line. For multidevice
configurations, t
REC
should be extended to accommo-
date the additional 1-Wire device input capacitance.
Alternatively, an interface that performs active pullup
during the 1-Wire recovery time such as the DS2482-x00
or DS2480B 1-Wire line drivers can be used.
RESISTOR MASTER DS2431-A1
t
RSTL
t
PDL
t
RSTH
t
PDH
MASTER Tx "RESET PULSE" MASTER Rx "PRESENCE PULSE"
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
ε
t
F
t
REC
t
MSP
Figure 10. Initialization Procedure: Reset and Presence Pulse