Datasheet
DS2411
3 of 12
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Timeslot Duration t
SLOT
Standard speed
65
µs
Overdrive V
CC
≥ 2.2V
8
Overdrive V
CC
≥ 1.5V
10
I/O PIN, 1-Wire RESET, PRESENCE DETECT CYCLE
Reset Low Time
t
RSTL
Standard speed
480
640
µs
Overdrive speed
60
80
Presence-Detect High Time t
PDH
Standard speed
15
60
µs
Overdrive V
CC
≥ 2.2V
2
6
Overdrive V
CC
≥ 1.5V
2
8.5
Presence-Detect Low Time t
PDL
Standard speed
60
240
µs
Overdrive V
CC
≥ 2.2V
8
24
Overdrive V
CC
≥ 1.5V
8
30
Presence-Detect Fall Time t
FPD
Standard speed (Note 10, 3)
0.4
8
µs
Overdrive speed (Note 10, 3)
0.05
1
Presence-Detect Sample
Time
t
MSP
Standard speed (Note 1)
60
75
µs
Overdrive V
CC
≥ 2.2V (Note 1)
6
10
Overdrive V
CC
≥ 1.5V (Note 1)
8.5
10
I/O PIN, 1-Wire WRITE
Write-0 Low Time t
W0L
Standard speed (Notes 1, 11, 13)
60
120
µs
Overdrive V
CC
≥ 2.2V
(Notes 1, 11, 13)
6 16
Overdrive V
CC
≥ 1.5V
(Notes 1, 11, 13)
8 16
Write-1 Low Time t
W1L
Standard speed (Notes 1, 11, 13)
5
15
µs
Overdrive speed (Notes 1, 11, 13)
1
2
I/O PIN, 1-Wire READ
Read Low Time t
RL
Standard speed (Notes 1, 12)
5
15 - δ
µs
Overdrive speed (Notes 1, 12)
1
2 - δ
Read Sample Time t
MSR
Standard speed (Notes 1, 12)
t
RL
+ δ
15
µs
Overdrive speed (Notes 1, 12)
t
RL
+ δ
2
Note 1: System requirement.
Note 2: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the
system and 1-Wire recovery times. The specified value here applies to systems with only
one device and with the minimum 1-Wire recovery times. For more heavily loaded
systems, an active pullup such as that found in the DS2480B may be required. Minimum
allowable pullup resistance is slightly greater than the value necessary to produce the
absolute maximum current (20mA) during 1-Wire low times at V
PUP
= 5.25V assuming
V
OL
= 0V.
Note 3: Not production tested.
Note 4: V
TL
and V
TH
are functions of V
CC
and temperature. The V
TH
and V
TL
maximum specifica-
tions are valid at V
CC
= 5.25V. In any case, V
TL
< V
TH
< V
CC
.
Note 5: Voltage below which during a falling edge on I/O, a logic ‘0’ is detected.
Note 6: Voltage above which during a rising edge on I/O, a logic ‘1’ is detected.
Note 7: After V
TH
is crossed during a rising edge on I/O, the voltage on I/O has to drop by V
HY
to
be detected as logic ‘0’.
Note 8: The I-V characteristic is linear for voltages less than 1V.