Datasheet

DS2408
4 of 39
Note 1:
System Requirement
Note 2:
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the
system and 1-Wire recovery times. The specified value here applies to systems with only one
device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an
active pullup such as that found in the DS2480B may be required.
Note 3:
If a 2.2kΩ resistor is used to pull up the data line to V
PUP
, 5µs after power has been applied,
the parasite capacitance does not affect normal communications.
Note 4:
Guaranteed by design—not production tested.
Note 5:
V
TL
and V
TH
are functions of the internal supply voltage, which in parasitic power mode, is a
function of V
PUP
and the 1-Wire recovery times. The V
TH
and V
TL
maximum specifications
are valid at V
PUP
= 5.25V. In any case, V
TL
< V
TH
< V
PUP
.
Note 6:
Voltage below which, during a falling edge on I/O, a logic '0' is detected.
Note 7:
The voltage on I/O needs to be less or equal to V
ILMAX
whenever the master drives the line
low.
Note 8:
Voltage above which, during a rising edge on I/O, a logic '1' is detected.
Note 9:
After V
TH
is crossed during a rising edge on I/O, the voltage on I/O has to drop by V
HY
to be
detected as logic '0'.
Note 10:
The I-V characteristic is linear for voltages less than 1V.
Note 11:
The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been reached
before.
Note 12:
Highlighted numbers are NOT in compliance with the published 1-Wire standards. See
comparison table below.
Note 13:
Interval during the negative edge on I/O at the beginning of a presence detect pulse between
the time at which the voltage is 90% of V
PUP
and the time at which the voltage is 10% of
V
PUP
.
Note 14:
ε in Figure 14 represents the time required for the pullup circuitry to pull the voltage on I/O
up from V
IL
to V
TH
. The actual maximum duration for the master to pull the line low is
t
W1LMAX
+ t
F
- ε and t
W0LMAX
+ t
F
- ε respectively.
Note 15:
δ in Figure 14 represents the time required for the pullup circuitry to pull the voltage on I/O
up from V
IL
to the input high threshold of the bus master. The actual maximum duration for
the master to pull the line low is t
RLMAX
+ t
F
.
Note 16:
Interval during the device-generated negative edge on any PIO pin or the RSTZ pin between
the time at which the voltage is 90% of V
PUP
and the time at which the voltage is 10% of
V
PUP
. PIO pullup resistor = 2.2k
Ω
.
Note 17:
Width of the narrowest pulse which trips the activity latch (for any PIO pin) or causes a reset
(for the RSTZ pin). For a pulse duration t
PW
: If t
PW
< t
PWMIN(min)
, the pulse will be rejected. If
t
PWMIN(min)
< t
PW
< t
PWMIN(max)
, the pulse may or may not be rejected. If t
PW
> t
PWMIN(max)
the
pulse will be recognized and latched.
Note 18:
Maximum instantaneous pulldown current through all port pins and the RSTZ pin combined.
No requirement for current balance among different pins.