Datasheet

DS2401
7 of 10
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 5
480μs ≤ t
RSTL
< ∞ *
480
μs ≤ t
RSTH
< ∞ (includes recovery time)
15
μs ≤ t
PDH
< 60μs
60
μs ≤ t
PDL
< 240μs
∗ In order not to mask interrupt signaling by other devices on the 1-Wire bus, t
RSTL
+ t
R
should always
be less than 960
μs.
READ/WRITE TIMING DIAGRAM Figure 6
Write-One Time Slot
60μs ≤ t
SLOT
< 120μs
1
μs ≤ t
LOW1
< 15μs
1
μs ≤ t
REC
< ∞
RESISTOR
MASTER
RESISTOR
MASTER
DS2401