Datasheet

DS21Q59 Quad E1 Transceiver
7 of 76
3. BLOCK DIAGRAM
Figure 3-1. Block Diagram
ALE(AS)/A5
RRING1
RECEIVE-SIDE
FRAMER
TRANSMIT-
SIDE
FORMATTER
TCLK1
TSER1
RSER1
SYSCLK1
RSYNC1
ELASTIC
STORE AND
IBO BUFFER
TRING1
TTIP1
JITTER ATTENUATOR
EITHER TRANSMIT OR RECEIVE PATH
RECEIVE
LINE I/F
CLOCK/DATA
RECOVERY
RTIP1
VCO/PLL
LINE I/F
TRANSMIT
DATA
CLOCK
SYNC
SYNC
CLOCK
DATA
IBO
BUFFER
DIVIDE-
BY-2/4/8
MCLK
TSYNC1
SYNC
CONTROL
BU Ck
MUX
Tx Ck
MUX
A
B
A
B
C
USER OUTPUT
SELECT
OUTA1
OUTB1
RCLK TRANSCEIVER 2
RCLK TRANSCEIVER 3
RCLK TRANSCEIVER 4
MUX
4/8/16MHz
SYNTHESIZER
BACKUP CLOCK MUX
TRANSCEIVERS 2, 3, 4
4/8/16MCK
REFCLK
SYSTEM CLOCK
INTERFACE
TRANSMIT
CLOCK SOURCE
TRANSCEIVER 1 OF 4
TRANSMIT
SIDE
RECEIVE
SIDE
LOCAL LOOPBACK
REMOTE LOOPBACK
FRAMER LOOPBAC
K
LOTC
DETECT
2.048MHz
D0–D7
/
AD0–AD7
TS1
IN
T
WR
(R/
W
)
RD
(
DS
)
C
S
A0–A4
PARALLEL AND TEST CONTROL PORT
(
ROUTED TO ALL BLOCKS
)
BTS1
BTS0
TS0
PBTS
AJACOI
AJACKI
ALTERNATE
JITTER
ATTENUATOR
Dallas
Semiconductor
DS21Q59